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HEADER 3 MIOS V1.7 hardware mods

<H1>MIOS V1.7 hardware mods</H1>

<P CLASS=INFO>This page summarizes all hardware modifications which are required from MIOS V1.7 and higher. The reasons for these changes are described in <A HREF="" TARGET="_blank">this forum article</A>.</P>

<H2>separate DIN/DOUT Shift Register clock</H2>

<P CLASS=INFO>With MIOS V1.7, the shift register clock of the DIN/DOUT chain <B>must</B> be a dedicated output, no other module or peripheral should be driven from the same pin (#22/RD3), otherwise you will notice flickering LEDs or not-working buttons/encoders.<BR>This means <B>no</B> change on the wiring to J8/J9, this means only that J10:SC shouldn't be used by any other module anymore.</P>

<H2>BankStick connection to the Core</H2>

<P CLASS=INFO>The IIC clock line J4:SC (BankStick) is now connected to pin (#28/RD5) of the core module. Thats an easy change, since it's normaly an isolated cable. Take a look into the <A HREF="mbhp/mbhp_core.pdf">MBHP_CORE schematic</A> or the <A HREF="mbhp/mbhp_core.gif">MBHP_CORE PCB quick view</A> to locate the correct pin.<P>

<H2>SID module connection to the Core</H2>

<P CLASS=INFO>The SCLK line of the SID module has also to be connected to pin (#28/RD5) of the core module. Desolder the cable from junction CORE:J10:SC and solder it to CORE:J10:MD. See also <A HREF="mbhp/mbhp_sid_c64_psu.pdf">mbhp_sid_c64_psu.pdf</A>, <A HREF="mbhp/mbhp_4xsid_c64_psu.pdf">mbhp_4xsid_c64_psu.pdf</A> and <A HREF="mbhp/mbhp_4xsid_c64_psu_optimized.pdf">mbhp_4xsid_c64_psu_optimized.pdf</A>.</P>