Subversion Repositories svn.mios32

Rev

Rev 2088 | Rev 2268 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed

Rev 2088 Rev 2098
Line 1... Line 1...
1
// $Id: seq_cv.c 2088 2014-11-02 22:15:56Z tk $
1
// $Id: seq_cv.c 2098 2014-12-07 19:25:03Z tk $
2
/*
2
/*
3
 * CV functions of MIDIbox SEQ
3
 * CV functions of MIDIbox SEQ
4
 *
4
 *
5
 * ==========================================================================
5
 * ==========================================================================
6
 *
6
 *
Line 31... Line 31...
31
/////////////////////////////////////////////////////////////////////////////
31
/////////////////////////////////////////////////////////////////////////////
32
32
33
// for smokestacksproductions:
33
// for smokestacksproductions:
34
// mirror J5.A0 at P0.4 (J18, CAN port) since the original IO doesn't work on his LPCXPRESSO anymore
34
// mirror J5.A0 at P0.4 (J18, CAN port) since the original IO doesn't work on his LPCXPRESSO anymore
35
#define MIRROR_J5_A0_AT_J18 1
35
#define MIRROR_J5_A0_AT_J18 1
-
 
36
-
 
37
/////////////////////////////////////////////////////////////////////////////
-
 
38
// Global variables
-
 
39
/////////////////////////////////////////////////////////////////////////////
-
 
40
-
 
41
u16 seq_cv_clkout_divider[SEQ_CV_NUM_CLKOUT];
-
 
42
u8  seq_cv_clkout_pulsewidth[SEQ_CV_NUM_CLKOUT];
36
43
37
44
38
/////////////////////////////////////////////////////////////////////////////
45
/////////////////////////////////////////////////////////////////////////////
39
// Local variables
46
// Local variables
40
/////////////////////////////////////////////////////////////////////////////
47
/////////////////////////////////////////////////////////////////////////////
41
48
42
static u8 gates;
49
static u8 gates;
43
static u8 gate_inversion_mask;
50
static u8 gate_inversion_mask;
44
51
45
static u8 sync_clk_pulsewidth;
52
static u8 seq_cv_clkout_pulse_ctr[SEQ_CV_NUM_CLKOUT];
46
static u16 sync_clk_divider;
-
 
47
53
48
// each channel has an own notestack
54
// each channel has an own notestack
49
static notestack_t cv_notestack[SEQ_CV_NUM];
55
static notestack_t cv_notestack[SEQ_CV_NUM];
50
static notestack_item_t cv_notestack_items[SEQ_CV_NUM][SEQ_CV_NOTESTACK_SIZE];
56
static notestack_item_t cv_notestack_items[SEQ_CV_NUM][SEQ_CV_NOTESTACK_SIZE];
51
57
Line 95... Line 101...
95
#endif
101
#endif
96
102
97
  // initialize AOUT driver
103
  // initialize AOUT driver
98
  AOUT_Init(0);
104
  AOUT_Init(0);
99
105
100
  // initial pulsewidth and divider for DIN clock
106
  // initial pulsewidth and divider for clock outputs
-
 
107
  {
-
 
108
      int clkout;
-
 
109
-
 
110
      for(clkout=0; clkout<SEQ_CV_NUM_CLKOUT; ++clkout) {
101
  sync_clk_pulsewidth = 1;
111
    seq_cv_clkout_pulsewidth[clkout] = 1;
102
  sync_clk_divider = 16; // 24 ppqn
112
    seq_cv_clkout_divider[clkout] = 16; // 24 ppqn
-
 
113
    seq_cv_clkout_pulse_ctr[clkout] = 0;
-
 
114
      }
-
 
115
  }
103
116
104
  // reset all channels
117
  // reset all channels
105
  SEQ_CV_ResetAllChannels();
118
  SEQ_CV_ResetAllChannels();
106
119
107
  return 0; // no error
120
  return 0; // no error
Line 302... Line 315...
302
315
303
316
304
/////////////////////////////////////////////////////////////////////////////
317
/////////////////////////////////////////////////////////////////////////////
305
// Get/Set DIN Clock Pulsewidth
318
// Get/Set DIN Clock Pulsewidth
306
/////////////////////////////////////////////////////////////////////////////
319
/////////////////////////////////////////////////////////////////////////////
307
s32 SEQ_CV_ClkPulseWidthSet(u8 width)
320
s32 SEQ_CV_ClkPulseWidthSet(u8 clkout, u8 width)
308
{
321
{
-
 
322
  if( clkout >= SEQ_CV_NUM_CLKOUT )
-
 
323
    return -1; // invalid clkout
-
 
324
309
  sync_clk_pulsewidth = width;
325
  seq_cv_clkout_pulsewidth[clkout] = width;
310
  return 0; // no error
326
  return 0; // no error
311
}
327
}
312
328
313
u8 SEQ_CV_ClkPulseWidthGet(void)
329
u8 SEQ_CV_ClkPulseWidthGet(u8 clkout)
314
{
330
{
315
  return sync_clk_pulsewidth;
331
  return seq_cv_clkout_pulsewidth[clkout];
316
}
332
}
317
333
318
334
319
/////////////////////////////////////////////////////////////////////////////
335
/////////////////////////////////////////////////////////////////////////////
320
// Get/Set DIN Clock Divider
336
// Get/Set DIN Clock Divider
321
/////////////////////////////////////////////////////////////////////////////
337
/////////////////////////////////////////////////////////////////////////////
322
s32 SEQ_CV_ClkDividerSet(u16 div)
338
s32 SEQ_CV_ClkDividerSet(u8 clkout, u16 div)
323
{
339
{
-
 
340
  if( clkout >= SEQ_CV_NUM_CLKOUT )
-
 
341
    return -1; // invalid clkout
-
 
342
324
  sync_clk_divider = div;
343
  seq_cv_clkout_divider[clkout] = div;
325
  return 0; // no error
344
  return 0; // no error
326
}
345
}
327
346
328
u16 SEQ_CV_ClkDividerGet(void)
347
u16 SEQ_CV_ClkDividerGet(u8 clkout)
329
{
348
{
330
  return sync_clk_divider;
349
  return seq_cv_clkout_divider[clkout];
-
 
350
}
-
 
351
-
 
352
-
 
353
/////////////////////////////////////////////////////////////////////////////
-
 
354
// Trigger a clock line
-
 
355
/////////////////////////////////////////////////////////////////////////////
-
 
356
s32 SEQ_CV_Clk_Trigger(u8 clkout)
-
 
357
{
-
 
358
  if( clkout >= SEQ_CV_NUM_CLKOUT )
-
 
359
    return -1; // invalid clkout
-
 
360
-
 
361
  seq_cv_clkout_pulse_ctr[clkout] = seq_cv_clkout_pulsewidth[clkout] + 1;
-
 
362
  return 0; // no error
331
}
363
}
332
364
333
365
334
/////////////////////////////////////////////////////////////////////////////
366
/////////////////////////////////////////////////////////////////////////////
335
// Updates all CV channels and gates
367
// Updates all CV channels and gates
Line 337... Line 369...
337
s32 SEQ_CV_Update(void)
369
s32 SEQ_CV_Update(void)
338
{
370
{
339
  static u8 last_gates = 0xff; // to force an update
371
  static u8 last_gates = 0xff; // to force an update
340
  static u8 last_start_stop = 0xff; // to force an update
372
  static u8 last_start_stop = 0xff; // to force an update
341
373
-
 
374
  u8 start_stop = SEQ_BPM_IsRunning();
-
 
375
-
 
376
  // Clock outputs
-
 
377
  // Note: a clock output acts as start/stop if clock divider set to 0
342
  u8 clk_sr_value = 0;
378
  u8 clk_sr_value = 0;
-
 
379
  {
-
 
380
    int clkout;
-
 
381
    u16 *clk_divider = (u16 *)&seq_cv_clkout_divider[0];
-
 
382
    u8 *pulse_ctr = (u8 *)&seq_cv_clkout_pulse_ctr[0];
-
 
383
    for(clkout=0; clkout<SEQ_CV_NUM_CLKOUT; ++clkout, ++clk_divider, ++pulse_ctr) {
-
 
384
      if( !*clk_divider && start_stop ) {
-
 
385
    clk_sr_value |= (1 << clkout);
-
 
386
      }
343
387
344
  // Start/Stop at J5C.A9
388
      if( *pulse_ctr ) {
-
 
389
    *pulse_ctr -= 1;
345
  u8 start_stop = SEQ_BPM_IsRunning();
390
    clk_sr_value |= (1 << clkout);
-
 
391
      }
-
 
392
    }
-
 
393
  }
346
394
-
 
395
  // Update Clock SR
347
  if( start_stop )
396
  if( seq_hwcfg_clk_sr )
348
    clk_sr_value |= 0xf0; // DOUT_SR.D3..D0
397
    MIOS32_DOUT_SRSet(seq_hwcfg_clk_sr-1, clk_sr_value);
349
398
-
 
399
  // Additional IO: Start/Stop at J5C.A9
350
  if( start_stop != last_start_stop ) {
400
  if( start_stop != last_start_stop ) {
351
    last_start_stop = start_stop;
401
    last_start_stop = start_stop;
352
402
353
#if defined(MIOS32_FAMILY_STM32F10x)
403
#if defined(MIOS32_FAMILY_STM32F10x)
354
    MIOS32_BOARD_J5_PinSet(9, start_stop);
404
    MIOS32_BOARD_J5_PinSet(9, start_stop);
Line 360... Line 410...
360
# warning "please adapt for this MIOS32_FAMILY"
410
# warning "please adapt for this MIOS32_FAMILY"
361
#endif
411
#endif
362
  }
412
  }
363
413
364
  // DIN Sync Pulse at J5C.A8
414
  // DIN Sync Pulse at J5C.A8
365
  if( seq_core_din_sync_pulse_ctr > 1 ) {
-
 
366
    clk_sr_value |= 0x0f; // D7..D4
-
 
367
-
 
368
#if defined(MIOS32_FAMILY_STM32F10x)
415
#if defined(MIOS32_FAMILY_STM32F10x)
369
    MIOS32_BOARD_J5_PinSet(8, 1);
416
  MIOS32_BOARD_J5_PinSet(8, (clk_sr_value & 1));
370
#elif defined(MIOS32_FAMILY_STM32F4xx)
417
#elif defined(MIOS32_FAMILY_STM32F4xx)
371
    MIOS32_BOARD_J10_PinSet(8, 1);
418
  MIOS32_BOARD_J10_PinSet(8, (clk_sr_value & 1));
372
#elif defined(MIOS32_FAMILY_LPC17xx)
419
#elif defined(MIOS32_FAMILY_LPC17xx)
373
    MIOS32_BOARD_J28_PinSet(0, 1);
420
  MIOS32_BOARD_J28_PinSet(0, (clk_sr_value & 1));
374
#else
421
#else
375
# warning "please adapt for this MIOS32_FAMILY"
422
# warning "please adapt for this MIOS32_FAMILY"
376
#endif
423
#endif
377
    --seq_core_din_sync_pulse_ctr;
-
 
378
  } else if( seq_core_din_sync_pulse_ctr == 1 ) {
-
 
379
#if defined(MIOS32_FAMILY_STM32F10x)
-
 
380
    MIOS32_BOARD_J5_PinSet(8, 0);
-
 
381
#elif defined(MIOS32_FAMILY_STM32F4xx)
-
 
382
    MIOS32_BOARD_J10_PinSet(8, 0);
-
 
383
#elif defined(MIOS32_FAMILY_LPC17xx)
-
 
384
    MIOS32_BOARD_J28_PinSet(0, 0);
-
 
385
#else
-
 
386
# warning "please adapt for this MIOS32_FAMILY"
-
 
387
#endif
-
 
388
-
 
389
    seq_core_din_sync_pulse_ctr = 0;
-
 
390
  }
-
 
391
-
 
392
  // Clock SR
-
 
393
  if( seq_hwcfg_clk_sr )
-
 
394
    MIOS32_DOUT_SRSet(seq_hwcfg_clk_sr-1, clk_sr_value);
-
 
395
-
 
396
424
397
  // update J5 Outputs (forwarding AOUT digital pins for modules which don't support gates)
425
  // update J5 Outputs (forwarding AOUT digital pins for modules which don't support gates)
398
  // The MIOS32_BOARD_* function won't forward pin states if J5_ENABLED was set to 0
426
  // The MIOS32_BOARD_* function won't forward pin states if J5_ENABLED was set to 0
399
  u8 new_gates = gates ^ gate_inversion_mask;
427
  u8 new_gates = gates ^ gate_inversion_mask;
400
  if( new_gates != last_gates ) {
428
  if( new_gates != last_gates ) {