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// $Id: pic18f4620.c 50 2008-01-30 21:47:50Z tk $
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/*
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/*
4
 * pic18f4620.c - PIC18F4620 Device Library Source
2
 * pic18f4620.c - PIC18F4620 Device Library Sources
5
 *
3
 *
6
 * This file is part of the GNU PIC Library.
4
 * This file is part of the GNU PIC Library.
7
 *
5
 *
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6
 * September, 2006
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7
 * Added modifications by
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8
 *     Anton Strobl <a.strobl AT aws-it.at>
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9
 *
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10
 * September, 2006
-
 
11
 * Added based on existing PICs
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12
 *      Gary Plumbridge <gary AT phodex.net>
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13
 *
8
 * January, 2004
14
 * May, 2005
9
 * The GNU PIC Library is maintained by,
15
 * The GNU PIC Library is maintained by
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16
 *     Raphael Neider <rneider AT web.de>
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17
 *
-
 
18
 * originally designed by
10
 *  Vangelis Rokas <vrokas@otenet.gr>
19
 *     Vangelis Rokas <vrokas AT otenet.gr>
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20
 *
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21
 * $Id: pic18f4620.c 305 2008-05-01 08:33:09Z stryd_one $
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22
 *
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23
 * Modified by stryd.one@gmail for MIOS SDCC wrapper compliance: FSR0 registers swapped with FSR1
11
 *
24
 *
12
 * Modified by tk@midibox.org for MIOS SDCC wrapper compliance: FSR0 registers swapped with FSR1
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13
 *
25
 *
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 */
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 */
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#include "pic18f4620.h"
28
#include <pic18f4620.h>
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29
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30
__sfr __at (0xF80) PORTA;
-
 
31
volatile __PORTA_t __at (0xF80) PORTAbits;
-
 
32
-
 
33
__sfr __at (0xF81) PORTB;
-
 
34
volatile __PORTB_t __at (0xF81) PORTBbits;
-
 
35
-
 
36
__sfr __at (0xF82) PORTC;
-
 
37
volatile __PORTC_t __at (0xF82) PORTCbits;
-
 
38
-
 
39
__sfr __at (0xF83) PORTD;
-
 
40
volatile __PORTD_t __at (0xF83) PORTDbits;
-
 
41
-
 
42
__sfr __at (0xF84) PORTE;
-
 
43
volatile __PORTE_t __at (0xF84) PORTEbits;
-
 
44
-
 
45
__sfr __at (0xF89) LATA;
-
 
46
volatile __LATA_t __at (0xF89) LATAbits;
-
 
47
-
 
48
__sfr __at (0xF8A) LATB;
-
 
49
volatile __LATB_t __at (0xF8A) LATBbits;
-
 
50
-
 
51
__sfr __at (0xF8B) LATC;
-
 
52
volatile __LATC_t __at (0xF8B) LATCbits;
-
 
53
-
 
54
__sfr __at (0xF8C) LATD;
-
 
55
volatile __LATD_t __at (0xF8C) LATDbits;
-
 
56
-
 
57
__sfr __at (0xF8D) LATE;
-
 
58
volatile __LATE_t __at (0xF8D) LATEbits;
-
 
59
-
 
60
__sfr __at (0xF92) TRISA;
-
 
61
volatile __TRISA_t __at (0xF92) TRISAbits;
-
 
62
-
 
63
__sfr __at (0xF93) TRISB;
-
 
64
volatile __TRISB_t __at (0xF93) TRISBbits;
-
 
65
-
 
66
__sfr __at (0xF94) TRISC;
-
 
67
volatile __TRISC_t __at (0xF94) TRISCbits;
-
 
68
-
 
69
__sfr __at (0xF95) TRISD;
-
 
70
volatile __TRISD_t __at (0xF95) TRISDbits;
-
 
71
-
 
72
__sfr __at (0xF96) TRISE;
-
 
73
volatile __TRISE_t __at (0xF96) TRISEbits;
-
 
74
-
 
75
__sfr __at (0xF9B) OSCTUNE;
-
 
76
volatile __OSCTUNE_t __at (0xF9B) OSCTUNEbits;
-
 
77
-
 
78
__sfr __at (0xF9D) PIE1;
-
 
79
volatile __PIE1_t __at (0xF9D) PIE1bits;
-
 
80
-
 
81
__sfr __at (0xF9E) PIR1;
-
 
82
volatile __PIR1_t __at (0xF9E) PIR1bits;
-
 
83
-
 
84
__sfr __at (0xF9F) IPR1;
-
 
85
volatile __IPR1_t __at (0xF9F) IPR1bits;
-
 
86
-
 
87
__sfr __at (0xFA0) PIE2;
-
 
88
volatile __PIE2_t __at (0xFA0) PIE2bits;
-
 
89
-
 
90
__sfr __at (0xFA1) PIR2;
-
 
91
volatile __PIR2_t __at (0xFA1) PIR2bits;
-
 
92
-
 
93
__sfr __at (0xFA2) IPR2;
-
 
94
volatile __IPR2_t __at (0xFA2) IPR2bits;
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95
-
 
96
__sfr __at (0xFA6) EECON1;
-
 
97
volatile __EECON1_t __at (0xFA6) EECON1bits;
-
 
98
-
 
99
__sfr __at (0xFA7) EECON2;
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100
-
 
101
__sfr __at (0xFA8) EEDATA;
-
 
102
-
 
103
__sfr __at (0xFA9) EEADR;
-
 
104
-
 
105
__sfr __at (0xFAA) EEADRH;
-
 
106
-
 
107
__sfr __at (0xFAB) RCSTA;
-
 
108
volatile __RCSTA_t __at (0xFAB) RCSTAbits;
-
 
109
-
 
110
__sfr __at (0xFAC) TXSTA;
-
 
111
volatile __TXSTA_t __at (0xFAC) TXSTAbits;
-
 
112
-
 
113
__sfr __at (0xFAD) TXREG;
-
 
114
-
 
115
__sfr __at (0xFAE) RCREG;
-
 
116
-
 
117
__sfr __at (0xFAF) SPBRG;
-
 
118
-
 
119
__sfr __at (0xFB0) SPBRGH;
-
 
120
-
 
121
__sfr __at (0xFB1) T3CON;
-
 
122
volatile __T3CON_t __at (0xFB1) T3CONbits;
-
 
123
-
 
124
__sfr __at (0xFB2) TMR3L;
-
 
125
-
 
126
__sfr __at (0xFB3) TMR3H;
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127
-
 
128
__sfr __at (0xFB4) CMCON;
-
 
129
volatile __CMCON_t __at (0xFB4) CMCONbits;
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130
-
 
131
__sfr __at (0xFB5) CVRCON;
-
 
132
volatile __CVRCON_t __at (0xFB5) CVRCONbits;
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133
-
 
134
__sfr __at (0xFB6) ECCP1AS;
-
 
135
volatile __ECCP1AS_t __at (0xFB6) ECCP1ASbits;
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136
-
 
137
__sfr __at (0xFB7) PWM1CON;
-
 
138
volatile __PWM1CON_t __at (0xFB7) PWM1CONbits;
-
 
139
-
 
140
__sfr __at (0xFB8) BAUDCON;
-
 
141
volatile __BAUDCON_t __at (0xFB8) BAUDCONbits;
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142
-
 
143
__sfr __at (0xFBA) CCP2CON;
-
 
144
volatile __CCP2CON_t __at (0xFBA) CCP2CONbits;
-
 
145
-
 
146
__sfr __at (0xFBB) CCPR2L;
-
 
147
-
 
148
__sfr __at (0xFBC) CCPR2H;
-
 
149
-
 
150
__sfr __at (0xFBD) CCP1CON;
-
 
151
volatile __CCP1CON_t __at (0xFBD) CCP1CONbits;
-
 
152
-
 
153
__sfr __at (0xFBE) CCPR1L;
-
 
154
-
 
155
__sfr __at (0xFBF) CCPR1H;
-
 
156
-
 
157
__sfr __at (0xFC0) ADCON2;
-
 
158
volatile __ADCON2_t __at (0xFC0) ADCON2bits;
-
 
159
-
 
160
__sfr __at (0xFC1) ADCON1;
-
 
161
volatile __ADCON1_t __at (0xFC1) ADCON1bits;
-
 
162
-
 
163
__sfr __at (0xFC2) ADCON0;
-
 
164
volatile __ADCON0_t __at (0xFC2) ADCON0bits;
-
 
165
-
 
166
__sfr __at (0xFC3) ADRESL;
-
 
167
-
 
168
__sfr __at (0xFC4) ADRESH;
-
 
169
-
 
170
__sfr __at (0xFC5) SSPCON2;
-
 
171
volatile __SSPCON2_t __at (0xFC5) SSPCON2bits;
-
 
172
-
 
173
__sfr __at (0xFC6) SSPCON1;
-
 
174
volatile __SSPCON1_t __at (0xFC6) SSPCON1bits;
-
 
175
-
 
176
__sfr __at (0xFC7) SSPSTAT;
-
 
177
volatile __SSPSTAT_t __at (0xFC7) SSPSTATbits;
-
 
178
-
 
179
__sfr __at (0xFC8) SSPADD;
-
 
180
-
 
181
__sfr __at (0xFC9) SSPBUF;
-
 
182
-
 
183
__sfr __at (0xFCA) T2CON;
-
 
184
volatile __T2CON_t __at (0xFCA) T2CONbits;
-
 
185
-
 
186
__sfr __at (0xFCB) PR2;
-
 
187
-
 
188
__sfr __at (0xFCC) TMR2;
-
 
189
-
 
190
__sfr __at (0xFCD) T1CON;
-
 
191
volatile __T1CON_t __at (0xFCD) T1CONbits;
-
 
192
-
 
193
__sfr __at (0xFCE) TMR1L;
-
 
194
-
 
195
__sfr __at (0xFCF) TMR1H;
-
 
196
-
 
197
__sfr __at (0xFD0) RCON;
-
 
198
volatile __RCON_t __at (0xFD0) RCONbits;
17
199
18
sfr at 0xf80 PORTA;
200
__sfr __at (0xFD1) WDTCON;
19
volatile __PORTAbits_t at 0xf80 PORTAbits;
201
volatile __WDTCON_t __at (0xFD1) WDTCONbits;
20
202
21
sfr at 0xf81 PORTB;
203
__sfr __at (0xFD2) HLVDCON;
22
volatile __PORTBbits_t at 0xf81 PORTBbits;
204
volatile __HLVDCON_t __at (0xFD2) HLVDCONbits;
23
205
24
sfr at 0xf82 PORTC;
206
__sfr __at (0xFD3) OSCCON;
25
volatile __PORTCbits_t at 0xf82 PORTCbits;
207
volatile __OSCCON_t __at (0xFD3) OSCCONbits;
26
208
27
sfr at 0xf83 PORTD;
209
__sfr __at (0xFD5) T0CON;
28
volatile __PORTDbits_t at 0xf83 PORTDbits;
210
volatile __T0CON_t __at (0xFD5) T0CONbits;
29
211
30
sfr at 0xf84 PORTE;
212
__sfr __at (0xFD6) TMR0L;
31
volatile __PORTEbits_t at 0xf84 PORTEbits;
-
 
32
213
33
sfr at 0xf89 LATA;
214
__sfr __at (0xFD7) TMR0H;
34
volatile __LATAbits_t at 0xf89 LATAbits;
-
 
35
215
36
sfr at 0xf8a LATB;
216
__sfr __at (0xFD8) STATUS;
37
volatile __LATBbits_t at 0xf8a LATBbits;
217
volatile __STATUS_t __at (0xFD8) STATUSbits;
38
218
39
sfr at 0xf8b LATC;
219
__sfr __at (0xFD9) FSR2L;
40
volatile __LATCbits_t at 0xf8b LATCbits;
-
 
41
220
42
sfr at 0xf8c LATD;
221
__sfr __at (0xFDA) FSR2H;
43
volatile __LATDbits_t at 0xf8c LATDbits;
222
volatile __FSR2H_t __at (0xFDA) FSR2Hbits;
44
223
45
sfr at 0xf8d LATE;
224
__sfr __at (0xFDB) PLUSW2;
46
volatile __LATEbits_t at 0xf8d LATEbits;
-
 
47
225
48
sfr at 0xf92 TRISA;
226
__sfr __at (0xFDC) PREINC2;
49
volatile __TRISAbits_t at 0xf92 TRISAbits;
-
 
50
227
51
sfr at 0xf93 TRISB;
228
__sfr __at (0xFDD) POSTDEC2;
52
volatile __TRISBbits_t at 0xf93 TRISBbits;
-
 
53
229
54
sfr at 0xf94 TRISC;
230
__sfr __at (0xFDE) POSTINC2;
55
volatile __TRISCbits_t at 0xf94 TRISCbits;
-
 
56
231
57
sfr at 0xf95 TRISD;
232
__sfr __at (0xFDF) INDF2;
58
volatile __TRISDbits_t at 0xf95 TRISDbits;
-
 
59
233
60
sfr at 0xf96 TRISE;
234
__sfr __at (0xFE0) BSR;
61
volatile __TRISEbits_t at 0xf96 TRISEbits;
235
volatile __BSR_t __at (0xFE0) BSRbits;
62
236
63
sfr at 0xf9d PIE1;
237
__sfr __at (0xFE1) FSR0L;
64
volatile __PIE1bits_t at 0xf9d PIE1bits;
-
 
65
238
66
sfr at 0xf9e PIR1;
239
__sfr __at (0xFE2) FSR0H;
67
volatile __PIR1bits_t at 0xf9e PIR1bits;
240
volatile __FSR0H_t __at (0xFE2) FSR0Hbits;
68
241
69
sfr at 0xf9f IPR1;
242
__sfr __at (0xFE3) PLUSW0;
70
volatile __IPR1bits_t at 0xf9f IPR1bits;
-
 
71
243
72
sfr at 0xfa0 PIE2;
244
__sfr __at (0xFE4) PREINC0;
73
volatile __PIE2bits_t at 0xfa0 PIE2bits;
-
 
74
245
75
sfr at 0xfa1 PIR2;
246
__sfr __at (0xFE5) POSTDEC0;
76
volatile __PIR2bits_t at 0xfa1 PIR2bits;
-
 
77
247
78
sfr at 0xfa2 IPR2;
248
__sfr __at (0xFE6) POSTINC0;
79
volatile __IPR2bits_t at 0xfa2 IPR2bits;
-
 
80
249
81
sfr at 0xfa6 EECON1;
250
__sfr __at (0xFE7) INDF0;
82
volatile __EECON1bits_t at 0xfa6 EECON1bits;
-
 
83
251
84
sfr at 0xfa7 EECON2;
-
 
85
sfr at 0xfa8 EEDATA;
252
__sfr __at (0xFE8) WREG;
86
sfr at 0xfa9 EEADR;
-
 
87
sfr at 0xfab RCSTA;
-
 
88
volatile __RCSTAbits_t at 0xfab RCSTAbits;
-
 
89
253
90
sfr at 0xfac TXSTA;
254
__sfr __at (0xFE9) FSR1L;
91
volatile __TXSTAbits_t at 0xfac TXSTAbits;
-
 
92
255
93
sfr at 0xfad TXREG;
-
 
94
sfr at 0xfae RCREG;
256
__sfr __at (0xFEA) FSR1H;
95
sfr at 0xfaf SPBRG;
-
 
96
sfr at 0xfb1 T3CON;
-
 
97
volatile __T3CONbits_t at 0xfb1 T3CONbits;
257
volatile __FSR1H_t __at (0xFEA) FSR1Hbits;
98
258
99
sfr at 0xfb2 TMR3L;
-
 
100
sfr at 0xfb3 TMR3H;
259
__sfr __at (0xFEB) PLUSW1;
101
sfr at 0xfba CCP2CON;
-
 
102
volatile __CCP2CONbits_t at 0xfba CCP2CONbits;
-
 
103
260
104
sfr at 0xfbb CCPR2L;
-
 
105
sfr at 0xfbc CCPR2H;
-
 
106
sfr at 0xfbd CCP1CON;
261
__sfr __at (0xFEC) PREINC1;
107
volatile __CCP1CONbits_t at 0xfbd CCP1CONbits;
-
 
108
262
109
sfr at 0xfbe CCPR1L;
-
 
110
sfr at 0xfbf CCPR1H;
-
 
111
sfr at 0xfc1 ADCON1;
263
__sfr __at (0xFED) POSTDEC1;
112
volatile __ADCON1bits_t at 0xfc1 ADCON1bits;
-
 
113
264
114
sfr at 0xfc2 ADCON0;
265
__sfr __at (0xFEE) POSTINC1;
115
volatile __ADCON0bits_t at 0xfc2 ADCON0bits;
-
 
116
266
117
sfr at 0xfc3 ADRESL;
-
 
118
sfr at 0xfc4 ADRESH;
267
__sfr __at (0xFEF) INDF1;
119
sfr at 0xfc5 SSPCON2;
-
 
120
volatile __SSPCON2bits_t at 0xfc5 SSPCON2bits;
-
 
121
268
122
sfr at 0xfc6 SSPCON1;
269
__sfr __at (0xFF0) INTCON3;
123
volatile __SSPCON1bits_t at 0xfc6 SSPCON1bits;
270
volatile __INTCON3_t __at (0xFF0) INTCON3bits;
124
271
125
sfr at 0xfc7 SSPSTAT;
272
__sfr __at (0xFF1) INTCON2;
126
volatile __SSPSTATbits_t at 0xfc7 SSPSTATbits;
273
volatile __INTCON2_t __at (0xFF1) INTCON2bits;
127
274
128
sfr at 0xfc8 SSPADD;
-
 
129
sfr at 0xfc9 SSPBUF;
-
 
130
sfr at 0xfca T2CON;
275
__sfr __at (0xFF2) INTCON;
131
volatile __T2CONbits_t at 0xfca T2CONbits;
276
volatile __INTCON_t __at (0xFF2) INTCONbits;
132
277
133
sfr at 0xfcb PR2;
278
__sfr __at (0xFF3) PRODL;
134
sfr at 0xfcc TMR2;
-
 
135
sfr at 0xfcd T1CON;
-
 
136
volatile __T1CONbits_t at 0xfcd T1CONbits;
-
 
137
279
138
sfr at 0xfce TMR1L;
-
 
139
sfr at 0xfcf TMR1H;
280
__sfr __at (0xFF4) PRODH;
140
sfr at 0xfd0 RCON;
-
 
141
volatile __RCONbits_t at 0xfd0 RCONbits;
-
 
142
281
143
sfr at 0xfd1 WDTCON;
282
__sfr __at (0xFF5) TABLAT;
144
volatile __WDTCONbits_t at 0xfd1 WDTCONbits;
-
 
145
283
146
sfr at 0xfd2 LVDCON;
284
__sfr __at (0xFF6) TBLPTRL;
147
volatile __LVDCONbits_t at 0xfd2 LVDCONbits;
-
 
148
285
149
sfr at 0xfd3 OSCCON;
286
__sfr __at (0xFF7) TBLPTRH;
150
volatile __OSCCONbits_t at 0xfd3 OSCCONbits;
-
 
151
287
152
sfr at 0xfd5 T0CON;
288
__sfr __at (0xFF8) TBLPTRU;
153
volatile __T0CONbits_t at 0xfd5 T0CONbits;
289
volatile __TBLPTRU_t __at (0xFF8) TBLPTRUbits;
154
290
155
sfr at 0xfd6 TMR0L;
291
__sfr __at (0xFF9) PCL;
156
sfr at 0xfd7 TMR0H;
-
 
157
sfr at 0xfd8 STATUS;
-
 
158
volatile __STATUSbits_t at 0xfd8 STATUSbits;
-
 
159
292
160
sfr at 0xfd9 FSR2L;
-
 
161
sfr at 0xfda FSR2H;
-
 
162
sfr at 0xfdb PLUSW2;
293
__sfr __at (0xFFA) PCLATH;
163
sfr at 0xfdc PREINC2;
-
 
164
sfr at 0xfdd POSTDEC2;
-
 
165
sfr at 0xfde POSTINC2;
-
 
166
sfr at 0xfdf INDF2;
-
 
167
sfr at 0xfe0 BSR;
-
 
168
sfr at 0xfe9 FSR1L;         // swapped with FSR0L for MIOS wrapper compliance
-
 
169
sfr at 0xfea FSR1H;         // swapped with FSR0H for MIOS wrapper compliance
-
 
170
sfr at 0xfeb PLUSW1;        // swapped with PLUSW0 for MIOS wrapper compliance
-
 
171
sfr at 0xfec PREINC1;       // swapped with PREINC0 for MIOS wrapper compliance
-
 
172
sfr at 0xfed POSTDEC1;      // swapped with POSTDEC0 for MIOS wrapper compliance
-
 
173
sfr at 0xfee POSTINC1;      // swapped with POSTINC0 for MIOS wrapper compliance
-
 
174
sfr at 0xfef INDF1;         // swapped with INDF0 for MIOS wrapper compliance
-
 
175
sfr at 0xfe8 WREG;
-
 
176
sfr at 0xfe1 FSR0L;         // swapped with FSR1L for MIOS wrapper compliance
-
 
177
sfr at 0xfe2 FSR0H;         // swapped with FSR1H for MIOS wrapper compliance
-
 
178
sfr at 0xfe3 PLUSW0;        // swapped with PLUSW1 for MIOS wrapper compliance
-
 
179
sfr at 0xfe4 PREINC0;       // swapped with PREINC1 for MIOS wrapper compliance
-
 
180
sfr at 0xfe5 POSTDEC0;      // swapped with POSTDEC1 for MIOS wrapper compliance
-
 
181
sfr at 0xfe6 POSTINC0;      // swapped with POSTINC1 for MIOS wrapper compliance
-
 
182
sfr at 0xfe7 INDF0;         // swapped with INDF1 for MIOS wrapper compliance
-
 
183
sfr at 0xff0 INTCON3;
-
 
184
volatile __INTCON3bits_t at 0xff0 INTCON3bits;
294
volatile __PCLATH_t __at (0xFFA) PCLATHbits;
185
295
186
sfr at 0xff1 INTCON2;
296
__sfr __at (0xFFB) PCLATU;
187
volatile __INTCON2bits_t at 0xff1 INTCON2bits;
297
volatile __PCLATU_t __at (0xFFB) PCLATUbits;
188
298
189
sfr at 0xff2 INTCON;
299
__sfr __at (0xFFC) STKPTR;
190
volatile __INTCONbits_t at 0xff2 INTCONbits;
300
volatile __STKPTR_t __at (0xFFC) STKPTRbits;
191
301
192
sfr at 0xff3 PRODL;
302
__sfr __at (0xFFD) TOSL;
193
sfr at 0xff4 PRODH;
-
 
194
sfr at 0xff5 TABLAT;
-
 
195
sfr at 0xff6 TBLPTRL;
-
 
196
sfr at 0xff7 TBLPTRH;
-
 
197
sfr at 0xff8 TBLPTRU;
-
 
198
sfr at 0xff9 PCL;
-
 
199
sfr at 0xffa PCLATH;
-
 
200
sfr at 0xffb PCLATU;
-
 
201
sfr at 0xffc STKPTR;
-
 
202
volatile __STKPTRbits_t at 0xffc STKPTRbits;
-
 
203
303
204
sfr at 0xffd TOSL;
-
 
205
sfr at 0xffe TOSH;
304
__sfr __at (0xFFE) TOSH;
206
sfr at 0xfff TOSU;
-
 
207
305
-
 
306
__sfr __at (0xFFF) TOSU;
-
 
307
volatile __TOSU_t __at (0xFFF) TOSUbits;
208
308