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<application name>
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===============================================================================
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FRAM Module Test application
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Copyright (C) <year>  <name> (<email>)
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===============================================================================
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Licensed for personal non-commercial use only.
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Copyright (C) 2009 Matthias M├Ąchler (maechler@mm-computing.ch / thismaechler@gmx.ch)
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All other rights reserved.
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Licensed for personal non-commercial use only.
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===============================================================================
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All other rights reserved.
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===============================================================================
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A precompiled binary is already part of this package:
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   o project.hex (can be loaded into MIOS Studio)
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A precompiled binary is already part of this package:
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===============================================================================
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===============================================================================
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Required hardware:
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   o one MBHP_CORE module
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Required hardware:
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   o one MBHP_CORE module
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   o one FRAM module
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   o one LCD display
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Optional hardware:
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   o 
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Optional hardware:
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   o one DIN module with six buttons (pins 0 - 5)
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===============================================================================
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===============================================================================
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<description>
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The application uses the FRAM-module driver to test 1 - 32 connected 
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FRAM-devices (Ramtron FM24C64 / FM24C256 / FM24C512). One FM24C512 acts like
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two FM24C256, therefor only max. 16 of these chips can be connected.
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To connect more than 8(4) devices, you need to enable multiplexing for the FRAM
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driver, and the device's SDA/SCL lines must connected to a analog multiplexer.
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Configuration
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--------------
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Be sure the correct address range and device count is given accoring to your 
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device. See defines and comments at the top of main.c
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If you don't change anything, the default for FRAM-moudule will be selected
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(J10 RC4: SCL, RC5: SDA, multiplexing disabled), in main.c 8 devices with
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and address range of 0x7FFF are configured. This equals 4 x FM24C512 or
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8 x FM24C256.
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If you use multiplexed devices, enable the define in the Makefile. All possible
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FRAM_DEFINES that you can change are prepared but commented out.
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If you use multiplexing:
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	FRAM_DEFINES += -DFRAM_MULTIPLEX_ENABLE=1
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If you want to connect your FRAM devices to the standard MIOS IIC port J4:
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	FRAM_DEFINES += -DFRAM_MIOS_IIC=1
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If you notice unstable communication to the device (very long connection cable,
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bad slew rates etc.), increase this value step by step and check if the problem
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disappears:
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	FRAM_DEFINES += -DFRAM_IIC_SLOWDOWN=1
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For further information about the pin assignments, default values and defines,
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refer the README.txt of the FRAM-module.
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Test phases
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--------------
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The application runs 8 test-phases in series. Each run tests the whole address
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range of each device. Test byte values will be generated in the following way:
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LSB(address+device_addr+test_phase_offset). This ensures that each device and
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each test phase has it's own test value offsets, to ensure that device and
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address will be selected correctly, and no values will be "inherit" from one
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phase to another. These are the phases:
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1. Test buffer write/read/compare:
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----
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	Buffers of 256 bytes will be written and immediately read after writing. This
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	test run uses FRAM high level functions. The read data will be compared to 
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	the test values written before.
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2. Test single byte write/read/compare:
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----
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	Single bytes will be written and immediately read after writing. The read
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	byte will be compared to the one that was written before. FRAM high level 
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	functions will be used for this test run.
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3. Test subsequent buffer write:
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----
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	Performs subsequent buffer write using FRAM low-level functions. In each 
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	session, 32 x 256byte buffers will be written, the whole device- and 
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	address range will be covered.
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4. Test subsequent buffer read/compare:
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----
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	Performs subsequent buffer read using FRAM low-level functions. In each 
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	session, 32 x 256byte buffers will be read, the whole device- and 
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	address range will be covered. The values read should be the ones that were written
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	in the last phase. They will be compared to the originally written values.
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	In this test run, problems with the multiplexer or the device addressing 
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	show up. This will *not* happen in test-run 2, because the data is read 
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	immediately after writing. The compare will not fail because the same wrong
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	device is selected as with the write. In subsequent write, the whole device-
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	and address range will be written in one run, and each 256bytes sector has 
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	its own test value start offset. Wrong device selection will cause overwriting
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	of data that will show up as error in this test run.
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	If you want to analyze the problem in deep, set the test_value_deviceaddr_only
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	define to 1. This will cause the program to write the device address to each
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	byte of the given device. On error abort, you see the value that was read
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	and the value it should equal to, this allows to analyze on which stage  
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	the chip selection fails (chip address selectors / multiplexer).
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5. Test subsequent single byte write:
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----
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	Performs subsequent byte write using FRAM low-level functions. In each 
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	session, 32 x 256bytes will be written, the whole device- and address range 
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	will be covered.
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6. Test subsequent byte read/compare:
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----
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	Performs subsequent byte read using FRAM low-level functions. In each 
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	session, 32 x 256bytes will be read, the whole device- and address range 
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	will be covered. The values read should be the ones that were written
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	in the last phase. They will be compared to the originally written values.
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7. Speed test subsequent buffer write:
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----
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	Performs subsequent buffer write using FRAM low-level functions. In each 
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	session, 32 x 256byte buffers will be written, the whole device- and 
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	address range will be covered. The buffer will not be initialized with
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	values, it doesn't matter what data will be written, instead the time needed
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	for the whole run will be measured and shows up at the end in case of
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	success.
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8. Speed test subsequent buffer read:
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----
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	Performs subsequent buffer read using FRAM low-level functions. In each 
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	session, 32 x 256byte buffers will be read, the whole device- and 
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	address range will be covered. No data compare will take place, instead
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	the time needed for the whole run will be measured and shows up at the 
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	test summary screen after finishing.
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If all the test runs finished successfully, you will see a (alternating) summary 
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screen that shows you following information
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* Success message
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* Device count / address range
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* Speed test results (in mS, time needed for the whole device/address range)
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In case of a error-abort, you also see alternating screens which show you
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* In which phase and at which operation the error occured. Possible operations
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  are: Begin Read, Begin Write, Write, Read/Compare.
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* Device- and memory-address at which the error occured
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* [FRAM_ERROR code and FRAM_REG value] or [Read byte value / Should-be value]
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Test phase triggering with buttons
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------------------------------------
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If you have a DIN module connected, you can trigger test phases with pin 0 (e.g.
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button push, pin to ground).
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pin 0: phase 1(buffer wr/rd/cp)
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pin 1: phase 2(byte wr/rd/cp)
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pin 2: phase 3(subseq. buffer wr)
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pin 3: phase 5(subseq. byte wr)
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pin 4: phase 7(speed test buffer wr)
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pin 5: phase 8(speed test buffer rd)
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The following phases will be performed continous. 
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Note that it would make no sense to trigger the phases 4 and 6, because they 
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read and compare the values written in phases 3/5 before.
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===============================================================================
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===============================================================================