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Rev 990 Rev 1102
Line 1... Line 1...
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; $Id: sid_se.inc 990 2011-05-02 19:39:46Z tk $
1
; $Id: sid_se.inc 1102 2012-12-30 20:39:10Z tk $
2
;
2
;
3
; MIDIbox SID
3
; MIDIbox SID
4
; Software Synthesizer Engine
4
; Software Synthesizer Engine
5
;  
5
;  
6
; Activate this #define to measure the performance with a scope
6
; Activate this #define to measure the performance with a scope
Line 135... Line 135...
135
SID_ENV_STATE_RELEASE1		EQU	5
135
SID_ENV_STATE_RELEASE1		EQU	5
136
SID_ENV_STATE_RELEASE2		EQU	6
136
SID_ENV_STATE_RELEASE2		EQU	6
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137
138
SID_ENS_CTRL1_CLK_SLAVE		EQU	0	; switch between MIDI clock master/slave
138
SID_ENS_CTRL1_CLK_SLAVE		EQU	0	; switch between MIDI clock master/slave
139
SID_ENS_CTRL1_CLK_AUTO		EQU	1	; automatic switching between master/slave
139
SID_ENS_CTRL1_CLK_AUTO		EQU	1	; automatic switching between master/slave
-
 
140
SID_ENS_CTRL1_CLK_OUT		EQU	3	; enable clock output
140
SID_ENS_CTRL1_FIL_LOG		EQU	4	; Select logarithmic scale for filter
141
SID_ENS_CTRL1_FIL_LOG		EQU	4	; Select logarithmic scale for filter
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SID_ENS_CTRL1_MONO		EQU	6	; SIDs are played mono
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SID_ENS_CTRL1_MONO		EQU	6	; SIDs are played mono
142
SID_ENS_CTRL1_DOR		EQU	7	; Disable automatic Oscillator Reset during patch change (could also be called DAORDPC flag ;)
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SID_ENS_CTRL1_DOR		EQU	7	; Disable automatic Oscillator Reset during patch change (could also be called DAORDPC flag ;)
143
144

144
SID_ENS_CTRL2_F2A		EQU	0	; forward Filter CutOff/Resonance to AOUTs
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SID_ENS_CTRL2_F2A		EQU	0	; forward Filter CutOff/Resonance to AOUTs
Line 294... Line 295...
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SIDSE_Clk_NoSlaveTrigger
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SIDSE_Clk_NoSlaveTrigger
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	;; handle FA event (MIDI clock start)
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	;; handle FA event (MIDI clock start)
297
	BRA_IFCLR SID_SE_STATE, SID_SE_STATE_MIDI_CLK_FA_REQ, BANKED, SIDSE_Clk_NoFA
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	BRA_IFCLR SID_SE_STATE, SID_SE_STATE_MIDI_CLK_FA_REQ, BANKED, SIDSE_Clk_NoFA
298
SIDSE_Clk_FA
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SIDSE_Clk_FA
-
 
300
	;; send to MIDI OUT?
-
 
301
	movff	SID_LOCAL_ENS + SID_ENSx_CTRL1, WREG
-
 
302
	BRA_IFCLR WREG, SID_ENS_CTRL1_CLK_OUT, ACCESS, SIDSE_Clk_FA_NoOut
-
 
303
SIDSE_Clk_FA_Out
-
 
304
	;; handled in USER_Tick
-
 
305
	SET_BSR	SID_CLK_SEND_FA
-
 
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	bsf	SID_CLK_SEND_FA, 0, BANKED
-
 
307
	SET_BSR	SID_BASE
-
 
308
SIDSE_Clk_FA_NoOut
-
 
309
299
	;; request not cleared here, because it's also used by Arp and sequencer
310
	;; request not cleared here, because it's also used by Arp and sequencer
300
	;; must be cleared at end of update cycle
311
	;; must be cleared at end of update cycle
301
	;; 	bcf	SID_SE_STATE, SID_SE_STATE_MIDI_CLK_FA_REQ, BANKED
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	;; 	bcf	SID_SE_STATE, SID_SE_STATE_MIDI_CLK_FA_REQ, BANKED
302
	;; reset counters
313
	;; reset counters
303
	clrf	SID_SE_GLOBAL_CLK_CTR, BANKED
314
	clrf	SID_SE_GLOBAL_CLK_CTR, BANKED
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354
	SET_BSR	SID_BASE
365
	SET_BSR	SID_BASE
355
SIDSE_Clk_Inc
366
SIDSE_Clk_Inc
356
367
357
	;; increment global clock counter (for Clk/6 and Clk/24 divider)
368
	;; increment global clock counter (for Clk/6 and Clk/24 divider)
358
	incf	SID_SE_GLOBAL_CLK_CTR, F, BANKED
369
	incf	SID_SE_GLOBAL_CLK_CTR, F, BANKED
-
 
370

-
 
371
	;; send to MIDI OUT?
-
 
372
	movf	SID_SE_GLOBAL_CLK_CTR, W, BANKED
-
 
373
	andlw	0x03
-
 
374
	bnz	SIDSE_Clk_F8_NoOut
-
 
375
	movff	SID_LOCAL_ENS + SID_ENSx_CTRL1, WREG
-
 
376
	BRA_IFCLR WREG, SID_ENS_CTRL1_CLK_OUT, ACCESS, SIDSE_Clk_F8_NoOut
-
 
377
SIDSE_Clk_F8_Out
-
 
378
	;; handled in USER_Tick
-
 
379
	SET_BSR	SID_CLK_SEND_F8_CTR
-
 
380
	incf	SID_CLK_SEND_F8_CTR, W, BANKED
-
 
381
	bz	SIDSE_Clk_F8_NoOut  ; counter is 0xff - not serviced...?
-
 
382
	incf	SID_CLK_SEND_F8_CTR, F, BANKED
-
 
383
SIDSE_Clk_F8_NoOut
-
 
384
	SET_BSR	SID_BASE
359

385
360
	;; reset lower nibble on each 6th clock, increment high nibble
386
	;; reset lower nibble on each 6th clock, increment high nibble
361
	movf	SID_SE_GLOBAL_CLK_CTR, W, BANKED
387
	movf	SID_SE_GLOBAL_CLK_CTR, W, BANKED
362
	andlw	0x0f
388
	andlw	0x0f
363
	xorlw	0x06
389
	xorlw	0x06
-
 
390
	bz	SIDSE_Clk_Inc_6th
-
 
391
-
 
392
	;; if 12 is reached, we also reset the subcounter
-
 
393
	;; previously it was at 6, but we need a value dividable by 4 for the SID_CLK_SEND_F8 function
-
 
394
	xorlw	0x0c ^ 0x06	; reset at 12
364
	bnz	SIDSE_Clk_Inc_Not6th
395
	bnz	SIDSE_Clk_Inc_Not6th
-
 
396
	movlw	0xf0
-
 
397
	andwf	SID_SE_GLOBAL_CLK_CTR, F, BANKED
365
SIDSE_Clk_Inc_6th
398
SIDSE_Clk_Inc_6th
366
	movf	SID_SE_GLOBAL_CLK_CTR, W, BANKED
399
	movf	SID_SE_GLOBAL_CLK_CTR, W, BANKED
367
	addlw	0x10
400
	addlw	0x10
368
	andlw	0xf0
-
 
369
	movwf	SID_SE_GLOBAL_CLK_CTR, BANKED
401
	movwf	SID_SE_GLOBAL_CLK_CTR, BANKED
370
SIDSE_Clk_Inc_Not6th
402
SIDSE_Clk_Inc_Not6th
371
403
372
	;; notify clock event
404
	;; notify clock event
373
	bsf	SID_SE_STATE, SID_SE_STATE_GLOBAL_CLK_EVENT, BANKED
405
	bsf	SID_SE_STATE, SID_SE_STATE_GLOBAL_CLK_EVENT, BANKED
Line 390... Line 422...
390
422
391
	;; propagate clock/4 event to trigger matrix on each 6th clock
423
	;; propagate clock/4 event to trigger matrix on each 6th clock
392
	lfsr	FSR1, SID_PATCH_BUFFER_SHADOW + SID_Ix_L_TRG_Cl6_BASE
424
	lfsr	FSR1, SID_PATCH_BUFFER_SHADOW + SID_Ix_L_TRG_Cl6_BASE
393
	movf	SID_SE_GLOBAL_CLK_CTR, W, BANKED
425
	movf	SID_SE_GLOBAL_CLK_CTR, W, BANKED
394
	andlw	0x0f
426
	andlw	0x0f
-
 
427
	bnz	SIDSE_Clk_Reset_NoClk4
395
	skpnz
428
SIDSE_Clk_Reset_Clk4
396
	rcall	SIDSE_Clk_Hlp_PropClkEvent
429
	rcall	SIDSE_Clk_Hlp_PropClkEvent
-
 
430
SIDSE_Clk_Reset_NoClk4
397
431
398
	;; propagate clock/16 event to trigger matrix on each 24th clock
432
	;; propagate clock/16 event to trigger matrix on each 24th clock
399
	lfsr	FSR1, SID_PATCH_BUFFER_SHADOW + SID_Ix_L_TRG_C24_BASE
433
	lfsr	FSR1, SID_PATCH_BUFFER_SHADOW + SID_Ix_L_TRG_C24_BASE
400
	movf	SID_SE_GLOBAL_CLK_CTR, W, BANKED
434
	movf	SID_SE_GLOBAL_CLK_CTR, W, BANKED
401
	andlw	0x30
435
	andlw	0x30