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Ignore whitespace Rev 678 → Rev 679

/trunk/apps/synthesizers/midibox_sid_v2/src/sid_par_table.inc
178,46 → 178,49
P_M_OSC123_8 EQU 0x0f
P_M_OSC123_12 EQU 0x10
P_M_OSC123_4L EQU 0x11
P_M_OSC123_6L EQU 0x12
P_M_OSC123_4U EQU 0x13
P_M_OSC123_PB EQU 0x14
P_M_MOD_PM8 EQU 0x15
P_M_MOD_B76 EQU 0x16
P_M_LFO_4U EQU 0x17
P_M_LFO_PM8 EQU 0x18
P_M_LFO_8 EQU 0x19
P_M_ENV_PM8 EQU 0x1a
P_M_ENV_8 EQU 0x1b
P_M_WT_6 EQU 0x1c
P_M_WT_7 EQU 0x1d
P_M_WT_POS EQU 0x1e
P_M_NOTE EQU 0x1f
P_M_OSC_INS_PM7 EQU 0x20
P_M_OSC_INS_PM8 EQU 0x21
P_M_OSC_INS_7 EQU 0x22
P_M_OSC_INS_8 EQU 0x23
P_M_OSC_INS_12 EQU 0x24
P_M_OSC_INS_4L EQU 0x25
P_M_OSC_INS_6L EQU 0x26
P_M_OSC_INS_4U EQU 0x27
P_M_OSC_INS_PB EQU 0x28
P_M_OSC_BL_PM7 EQU 0x29
P_M_OSC_BL_PM8 EQU 0x2a
P_M_OSC_BL_P8 EQU 0x2b
P_M_OSC_BL_7 EQU 0x2c
P_M_OSC_BL_8 EQU 0x2d
P_M_OSC_BL_12 EQU 0x2e
P_M_OSC_BL_4L EQU 0x2f
P_M_OSC_BL_6L EQU 0x30
P_M_OSC_BL_4U EQU 0x31
P_M_OSC_BL_PB EQU 0x32
P_M_OSC_BL_FIL12 EQU 0x33
P_M_OSC_BL_FIL8 EQU 0x34
P_M_DRM_8 EQU 0x35
P_M_DRM_PM8 EQU 0x36
P_M_DRM_4U EQU 0x37
P_M_DRM_4L EQU 0x38
P_M_NOTE_INS EQU 0x39
P_M_OSC123_5L EQU 0x12
P_M_OSC123_6L EQU 0x13
P_M_OSC123_4U EQU 0x14
P_M_OSC123_PB EQU 0x15
P_M_MOD_PM8 EQU 0x16
P_M_MOD_B76 EQU 0x17
P_M_LFO_4U EQU 0x18
P_M_LFO_PM8 EQU 0x19
P_M_LFO_8 EQU 0x1a
P_M_ENV_PM8 EQU 0x1b
P_M_ENV_8 EQU 0x1c
P_M_WT_6 EQU 0x1d
P_M_WT_7 EQU 0x1e
P_M_WT_POS EQU 0x1f
P_M_NOTE EQU 0x20
P_M_OSC_INS_PM7 EQU 0x21
P_M_OSC_INS_PM8 EQU 0x22
P_M_OSC_INS_7 EQU 0x23
P_M_OSC_INS_8 EQU 0x24
P_M_OSC_INS_12 EQU 0x25
P_M_OSC_INS_4L EQU 0x26
P_M_OSC_INS_5L EQU 0x27
P_M_OSC_INS_6L EQU 0x28
P_M_OSC_INS_4U EQU 0x29
P_M_OSC_INS_PB EQU 0x2a
P_M_OSC_BL_PM7 EQU 0x2b
P_M_OSC_BL_PM8 EQU 0x2c
P_M_OSC_BL_P8 EQU 0x2d
P_M_OSC_BL_7 EQU 0x2e
P_M_OSC_BL_8 EQU 0x2f
P_M_OSC_BL_12 EQU 0x30
P_M_OSC_BL_4L EQU 0x31
P_M_OSC_BL_5L EQU 0x32
P_M_OSC_BL_6L EQU 0x33
P_M_OSC_BL_4U EQU 0x34
P_M_OSC_BL_PB EQU 0x35
P_M_OSC_BL_FIL12 EQU 0x36
P_M_OSC_BL_FIL8 EQU 0x37
P_M_DRM_8 EQU 0x38
P_M_DRM_PM8 EQU 0x39
P_M_DRM_4U EQU 0x3a
P_M_DRM_4L EQU 0x3b
P_M_NOTE_INS EQU 0x3c
 
 
 
357,10 → 360,10
PAR_ENTRY P_S_ARP_SPEED, P_N_OSC123, P_M_OSC123_6L, SID_Ix_L_S1V2_BASE+SID_Ix_Vx_ARP_SPEED_DIV
PAR_ENTRY P_S_ARP_SPEED, P_N_OSC123, P_M_OSC123_6L, SID_Ix_L_S1V3_BASE+SID_Ix_Vx_ARP_SPEED_DIV
;; --[ 0x4c-0x4f ]-----------------------------------------------------------------------------
PAR_ENTRY P_S_ARP_GL, P_N_OSC123, P_M_OSC123_4L, SID_Ix_L_S1V1_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC123, P_M_OSC123_4L, SID_Ix_L_S1V1_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC123, P_M_OSC123_4L, SID_Ix_L_S1V2_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC123, P_M_OSC123_4L, SID_Ix_L_S1V3_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC123, P_M_OSC123_5L, SID_Ix_L_S1V1_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC123, P_M_OSC123_5L, SID_Ix_L_S1V1_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC123, P_M_OSC123_5L, SID_Ix_L_S1V2_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC123, P_M_OSC123_5L, SID_Ix_L_S1V3_BASE+SID_Ix_Vx_ARP_GL_RNG
;; --[ 0x50-0x53 ]-----------------------------------------------------------------------------
PAR_ENTRY P_S_PITCHBENDER,P_N_OSC123, P_M_OSC123_PB, SIDL_V1_BASE
PAR_ENTRY P_S_PITCHBENDER,P_N_OSC123, P_M_OSC123_PB, SIDL_V1_BASE
694,14 → 697,14
PAR_ENTRY P_S_ARP_SPEED, P_N_OSC_INS, P_M_OSC_INS_6L, SID_Ix_M_I5_BASE+SID_Ix_Vx_ARP_SPEED_DIV
PAR_ENTRY P_S_ARP_SPEED, P_N_OSC_INS, P_M_OSC_INS_6L, SID_Ix_M_I6_BASE+SID_Ix_Vx_ARP_SPEED_DIV
;; --[ 0x70-0x77 ]-----------------------------------------------------------------------------
PAR_ENTRY P_S_ARP_GL, P_N_OSC_INS, P_M_OSC_INS_4L, SID_Ix_M_I1_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_INS, P_M_OSC_INS_4L, SID_Ix_M_I1_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_INS, P_M_OSC_INS_4L, SID_Ix_M_I1_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_INS, P_M_OSC_INS_4L, SID_Ix_M_I2_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_INS, P_M_OSC_INS_4L, SID_Ix_M_I3_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_INS, P_M_OSC_INS_4L, SID_Ix_M_I4_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_INS, P_M_OSC_INS_4L, SID_Ix_M_I5_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_INS, P_M_OSC_INS_4L, SID_Ix_M_I6_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_INS, P_M_OSC_INS_5L, SID_Ix_M_I1_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_INS, P_M_OSC_INS_5L, SID_Ix_M_I1_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_INS, P_M_OSC_INS_5L, SID_Ix_M_I1_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_INS, P_M_OSC_INS_5L, SID_Ix_M_I2_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_INS, P_M_OSC_INS_5L, SID_Ix_M_I3_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_INS, P_M_OSC_INS_5L, SID_Ix_M_I4_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_INS, P_M_OSC_INS_5L, SID_Ix_M_I5_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_INS, P_M_OSC_INS_5L, SID_Ix_M_I6_BASE+SID_Ix_Vx_ARP_GL_RNG
;; --[ 0x78-0x7f ]-----------------------------------------------------------------------------
PAR_ENTRY P_S_PITCHBENDER,P_N_OSC_INS, P_M_OSC_INS_PB, 0
PAR_ENTRY P_S_PITCHBENDER,P_N_OSC_INS, P_M_OSC_INS_PB, 0
956,10 → 959,10
PAR_ENTRY P_S_ARP_SPEED, P_N_OSC_BL, P_M_OSC_BL_6L, SID_Ix_B_S1V1_BASE+SID_Ix_Vx_ARP_SPEED_DIV
PAR_ENTRY P_S_ARP_SPEED, P_N_OSC_BL, P_M_OSC_BL_6L, SID_Ix_B_S1V1_BASE+SID_Ix_Vx_ARP_SPEED_DIV
;; --[ 0x4c-0x4f ]-----------------------------------------------------------------------------
PAR_ENTRY P_S_ARP_GL, P_N_OSC_BL, P_M_OSC_BL_4L, SID_Ix_B_S1V1_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_BL, P_M_OSC_BL_4L, SID_Ix_B_S1V1_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_BL, P_M_OSC_BL_4L, SID_Ix_B_S1V1_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_BL, P_M_OSC_BL_4L, SID_Ix_B_S1V1_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_BL, P_M_OSC_BL_5L, SID_Ix_B_S1V1_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_BL, P_M_OSC_BL_5L, SID_Ix_B_S1V1_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_BL, P_M_OSC_BL_5L, SID_Ix_B_S1V1_BASE+SID_Ix_Vx_ARP_GL_RNG
PAR_ENTRY P_S_ARP_GL, P_N_OSC_BL, P_M_OSC_BL_5L, SID_Ix_B_S1V1_BASE+SID_Ix_Vx_ARP_GL_RNG
;; --[ 0x50-0x53 ]-----------------------------------------------------------------------------
PAR_ENTRY P_S_PITCHBENDER,P_N_OSC_BL, P_M_OSC_BL_PB, SIDL_V1_BASE
PAR_ENTRY P_S_PITCHBENDER,P_N_OSC_BL, P_M_OSC_BL_PB, SIDL_V1_BASE