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305 stryd_one 1
/*
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 * pic18f4620.c - PIC18F4620 Device Library Sources
3
 *
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 * This file is part of the GNU PIC Library.
305 stryd_one 5
 *
6
 * September, 2006
7
 * Added modifications by
8
 *     Anton Strobl <a.strobl AT aws-it.at>
9
 *
10
 * September, 2006
11
 * Added based on existing PICs
12
 *      Gary Plumbridge <gary AT phodex.net>
13
 *
14
 * May, 2005
15
 * The GNU PIC Library is maintained by
16
 *     Raphael Neider <rneider AT web.de>
17
 *
18
 * originally designed by
19
 *     Vangelis Rokas <vrokas AT otenet.gr>
20
 *
21
 * $Id: pic18f4620.c 305 2008-05-01 08:33:09Z stryd_one $
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 *
305 stryd_one 23
 * Modified by stryd.one@gmail for MIOS SDCC wrapper compliance: FSR0 registers swapped with FSR1
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 *
305 stryd_one 25
 *
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 */
27
 
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#include <pic18f4620.h>
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__sfr __at (0xF80) PORTA;
31
volatile __PORTA_t __at (0xF80) PORTAbits;
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305 stryd_one 33
__sfr __at (0xF81) PORTB;
34
volatile __PORTB_t __at (0xF81) PORTBbits;
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__sfr __at (0xF82) PORTC;
37
volatile __PORTC_t __at (0xF82) PORTCbits;
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305 stryd_one 39
__sfr __at (0xF83) PORTD;
40
volatile __PORTD_t __at (0xF83) PORTDbits;
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305 stryd_one 42
__sfr __at (0xF84) PORTE;
43
volatile __PORTE_t __at (0xF84) PORTEbits;
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305 stryd_one 45
__sfr __at (0xF89) LATA;
46
volatile __LATA_t __at (0xF89) LATAbits;
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305 stryd_one 48
__sfr __at (0xF8A) LATB;
49
volatile __LATB_t __at (0xF8A) LATBbits;
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__sfr __at (0xF8B) LATC;
52
volatile __LATC_t __at (0xF8B) LATCbits;
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__sfr __at (0xF8C) LATD;
55
volatile __LATD_t __at (0xF8C) LATDbits;
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305 stryd_one 57
__sfr __at (0xF8D) LATE;
58
volatile __LATE_t __at (0xF8D) LATEbits;
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305 stryd_one 60
__sfr __at (0xF92) TRISA;
61
volatile __TRISA_t __at (0xF92) TRISAbits;
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305 stryd_one 63
__sfr __at (0xF93) TRISB;
64
volatile __TRISB_t __at (0xF93) TRISBbits;
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305 stryd_one 66
__sfr __at (0xF94) TRISC;
67
volatile __TRISC_t __at (0xF94) TRISCbits;
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305 stryd_one 69
__sfr __at (0xF95) TRISD;
70
volatile __TRISD_t __at (0xF95) TRISDbits;
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305 stryd_one 72
__sfr __at (0xF96) TRISE;
73
volatile __TRISE_t __at (0xF96) TRISEbits;
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305 stryd_one 75
__sfr __at (0xF9B) OSCTUNE;
76
volatile __OSCTUNE_t __at (0xF9B) OSCTUNEbits;
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305 stryd_one 78
__sfr __at (0xF9D) PIE1;
79
volatile __PIE1_t __at (0xF9D) PIE1bits;
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__sfr __at (0xF9E) PIR1;
82
volatile __PIR1_t __at (0xF9E) PIR1bits;
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__sfr __at (0xF9F) IPR1;
85
volatile __IPR1_t __at (0xF9F) IPR1bits;
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__sfr __at (0xFA0) PIE2;
88
volatile __PIE2_t __at (0xFA0) PIE2bits;
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305 stryd_one 90
__sfr __at (0xFA1) PIR2;
91
volatile __PIR2_t __at (0xFA1) PIR2bits;
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305 stryd_one 93
__sfr __at (0xFA2) IPR2;
94
volatile __IPR2_t __at (0xFA2) IPR2bits;
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305 stryd_one 96
__sfr __at (0xFA6) EECON1;
97
volatile __EECON1_t __at (0xFA6) EECON1bits;
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305 stryd_one 99
__sfr __at (0xFA7) EECON2;
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305 stryd_one 101
__sfr __at (0xFA8) EEDATA;
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305 stryd_one 103
__sfr __at (0xFA9) EEADR;
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305 stryd_one 105
__sfr __at (0xFAA) EEADRH;
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305 stryd_one 107
__sfr __at (0xFAB) RCSTA;
108
volatile __RCSTA_t __at (0xFAB) RCSTAbits;
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305 stryd_one 110
__sfr __at (0xFAC) TXSTA;
111
volatile __TXSTA_t __at (0xFAC) TXSTAbits;
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305 stryd_one 113
__sfr __at (0xFAD) TXREG;
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305 stryd_one 115
__sfr __at (0xFAE) RCREG;
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305 stryd_one 117
__sfr __at (0xFAF) SPBRG;
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305 stryd_one 119
__sfr __at (0xFB0) SPBRGH;
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305 stryd_one 121
__sfr __at (0xFB1) T3CON;
122
volatile __T3CON_t __at (0xFB1) T3CONbits;
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305 stryd_one 124
__sfr __at (0xFB2) TMR3L;
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305 stryd_one 126
__sfr __at (0xFB3) TMR3H;
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305 stryd_one 128
__sfr __at (0xFB4) CMCON;
129
volatile __CMCON_t __at (0xFB4) CMCONbits;
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305 stryd_one 131
__sfr __at (0xFB5) CVRCON;
132
volatile __CVRCON_t __at (0xFB5) CVRCONbits;
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305 stryd_one 134
__sfr __at (0xFB6) ECCP1AS;
135
volatile __ECCP1AS_t __at (0xFB6) ECCP1ASbits;
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305 stryd_one 137
__sfr __at (0xFB7) PWM1CON;
138
volatile __PWM1CON_t __at (0xFB7) PWM1CONbits;
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305 stryd_one 140
__sfr __at (0xFB8) BAUDCON;
141
volatile __BAUDCON_t __at (0xFB8) BAUDCONbits;
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__sfr __at (0xFBA) CCP2CON;
144
volatile __CCP2CON_t __at (0xFBA) CCP2CONbits;
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305 stryd_one 146
__sfr __at (0xFBB) CCPR2L;
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305 stryd_one 148
__sfr __at (0xFBC) CCPR2H;
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__sfr __at (0xFBD) CCP1CON;
151
volatile __CCP1CON_t __at (0xFBD) CCP1CONbits;
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305 stryd_one 153
__sfr __at (0xFBE) CCPR1L;
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305 stryd_one 155
__sfr __at (0xFBF) CCPR1H;
156
 
157
__sfr __at (0xFC0) ADCON2;
158
volatile __ADCON2_t __at (0xFC0) ADCON2bits;
159
 
160
__sfr __at (0xFC1) ADCON1;
161
volatile __ADCON1_t __at (0xFC1) ADCON1bits;
162
 
163
__sfr __at (0xFC2) ADCON0;
164
volatile __ADCON0_t __at (0xFC2) ADCON0bits;
165
 
166
__sfr __at (0xFC3) ADRESL;
167
 
168
__sfr __at (0xFC4) ADRESH;
169
 
170
__sfr __at (0xFC5) SSPCON2;
171
volatile __SSPCON2_t __at (0xFC5) SSPCON2bits;
172
 
173
__sfr __at (0xFC6) SSPCON1;
174
volatile __SSPCON1_t __at (0xFC6) SSPCON1bits;
175
 
176
__sfr __at (0xFC7) SSPSTAT;
177
volatile __SSPSTAT_t __at (0xFC7) SSPSTATbits;
178
 
179
__sfr __at (0xFC8) SSPADD;
180
 
181
__sfr __at (0xFC9) SSPBUF;
182
 
183
__sfr __at (0xFCA) T2CON;
184
volatile __T2CON_t __at (0xFCA) T2CONbits;
185
 
186
__sfr __at (0xFCB) PR2;
187
 
188
__sfr __at (0xFCC) TMR2;
189
 
190
__sfr __at (0xFCD) T1CON;
191
volatile __T1CON_t __at (0xFCD) T1CONbits;
192
 
193
__sfr __at (0xFCE) TMR1L;
194
 
195
__sfr __at (0xFCF) TMR1H;
196
 
197
__sfr __at (0xFD0) RCON;
198
volatile __RCON_t __at (0xFD0) RCONbits;
199
 
200
__sfr __at (0xFD1) WDTCON;
201
volatile __WDTCON_t __at (0xFD1) WDTCONbits;
202
 
203
__sfr __at (0xFD2) HLVDCON;
204
volatile __HLVDCON_t __at (0xFD2) HLVDCONbits;
205
 
206
__sfr __at (0xFD3) OSCCON;
207
volatile __OSCCON_t __at (0xFD3) OSCCONbits;
208
 
209
__sfr __at (0xFD5) T0CON;
210
volatile __T0CON_t __at (0xFD5) T0CONbits;
211
 
212
__sfr __at (0xFD6) TMR0L;
213
 
214
__sfr __at (0xFD7) TMR0H;
215
 
216
__sfr __at (0xFD8) STATUS;
217
volatile __STATUS_t __at (0xFD8) STATUSbits;
218
 
219
__sfr __at (0xFD9) FSR2L;
220
 
221
__sfr __at (0xFDA) FSR2H;
222
volatile __FSR2H_t __at (0xFDA) FSR2Hbits;
223
 
224
__sfr __at (0xFDB) PLUSW2;
225
 
226
__sfr __at (0xFDC) PREINC2;
227
 
228
__sfr __at (0xFDD) POSTDEC2;
229
 
230
__sfr __at (0xFDE) POSTINC2;
231
 
232
__sfr __at (0xFDF) INDF2;
233
 
234
__sfr __at (0xFE0) BSR;
235
volatile __BSR_t __at (0xFE0) BSRbits;
236
 
237
__sfr __at (0xFE1) FSR0L;
238
 
239
__sfr __at (0xFE2) FSR0H;
240
volatile __FSR0H_t __at (0xFE2) FSR0Hbits;
241
 
242
__sfr __at (0xFE3) PLUSW0;
243
 
244
__sfr __at (0xFE4) PREINC0;
245
 
246
__sfr __at (0xFE5) POSTDEC0;
247
 
248
__sfr __at (0xFE6) POSTINC0;
249
 
250
__sfr __at (0xFE7) INDF0;
251
 
252
__sfr __at (0xFE8) WREG;
253
 
254
__sfr __at (0xFE9) FSR1L;
255
 
256
__sfr __at (0xFEA) FSR1H;
257
volatile __FSR1H_t __at (0xFEA) FSR1Hbits;
258
 
259
__sfr __at (0xFEB) PLUSW1;
260
 
261
__sfr __at (0xFEC) PREINC1;
262
 
263
__sfr __at (0xFED) POSTDEC1;
264
 
265
__sfr __at (0xFEE) POSTINC1;
266
 
267
__sfr __at (0xFEF) INDF1;
268
 
269
__sfr __at (0xFF0) INTCON3;
270
volatile __INTCON3_t __at (0xFF0) INTCON3bits;
271
 
272
__sfr __at (0xFF1) INTCON2;
273
volatile __INTCON2_t __at (0xFF1) INTCON2bits;
274
 
275
__sfr __at (0xFF2) INTCON;
276
volatile __INTCON_t __at (0xFF2) INTCONbits;
277
 
278
__sfr __at (0xFF3) PRODL;
279
 
280
__sfr __at (0xFF4) PRODH;
281
 
282
__sfr __at (0xFF5) TABLAT;
283
 
284
__sfr __at (0xFF6) TBLPTRL;
285
 
286
__sfr __at (0xFF7) TBLPTRH;
287
 
288
__sfr __at (0xFF8) TBLPTRU;
289
volatile __TBLPTRU_t __at (0xFF8) TBLPTRUbits;
290
 
291
__sfr __at (0xFF9) PCL;
292
 
293
__sfr __at (0xFFA) PCLATH;
294
volatile __PCLATH_t __at (0xFFA) PCLATHbits;
295
 
296
__sfr __at (0xFFB) PCLATU;
297
volatile __PCLATU_t __at (0xFFB) PCLATUbits;
298
 
299
__sfr __at (0xFFC) STKPTR;
300
volatile __STKPTR_t __at (0xFFC) STKPTRbits;
301
 
302
__sfr __at (0xFFD) TOSL;
303
 
304
__sfr __at (0xFFE) TOSH;
305
 
306
__sfr __at (0xFFF) TOSU;
307
volatile __TOSU_t __at (0xFFF) TOSUbits;
308