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/*
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 * pic18f452.c - PIC18F452 Device Library Source
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 *
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 * This file is part of the GNU PIC Library.
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 *
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 * January, 2004
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 * The GNU PIC Library is maintained by,
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 *  Vangelis Rokas <vrokas@otenet.gr>
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 *
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 * $Id: pic18f452.c 305 2008-05-01 08:33:09Z stryd_one $
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 *
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 * Modified by stryd.one@gmail for MIOS SDCC wrapper compliance: FSR0 registers swapped with FSR1
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 *
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 *
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 */
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#include <pic18f452.h>
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__sfr __at (0xf80) PORTA;
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volatile __PORTAbits_t __at (0xf80) PORTAbits;
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__sfr __at (0xf81) PORTB;
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volatile __PORTBbits_t __at (0xf81) PORTBbits;
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__sfr __at (0xf82) PORTC;
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volatile __PORTCbits_t __at (0xf82) PORTCbits;
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__sfr __at (0xf83) PORTD;
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volatile __PORTDbits_t __at (0xf83) PORTDbits;
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__sfr __at (0xf84) PORTE;
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volatile __PORTEbits_t __at (0xf84) PORTEbits;
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__sfr __at (0xf89) LATA;
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volatile __LATAbits_t __at (0xf89) LATAbits;
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__sfr __at (0xf8a) LATB;
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volatile __LATBbits_t __at (0xf8a) LATBbits;
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__sfr __at (0xf8b) LATC;
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volatile __LATCbits_t __at (0xf8b) LATCbits;
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__sfr __at (0xf8c) LATD;
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volatile __LATDbits_t __at (0xf8c) LATDbits;
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__sfr __at (0xf8d) LATE;
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volatile __LATEbits_t __at (0xf8d) LATEbits;
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__sfr __at (0xf92) TRISA;
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volatile __TRISAbits_t __at (0xf92) TRISAbits;
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__sfr __at (0xf93) TRISB;
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volatile __TRISBbits_t __at (0xf93) TRISBbits;
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__sfr __at (0xf94) TRISC;
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volatile __TRISCbits_t __at (0xf94) TRISCbits;
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__sfr __at (0xf95) TRISD;
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volatile __TRISDbits_t __at (0xf95) TRISDbits;
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__sfr __at (0xf96) TRISE;
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volatile __TRISEbits_t __at (0xf96) TRISEbits;
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__sfr __at (0xf9d) PIE1;
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volatile __PIE1bits_t __at (0xf9d) PIE1bits;
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__sfr __at (0xf9e) PIR1;
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volatile __PIR1bits_t __at (0xf9e) PIR1bits;
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__sfr __at (0xf9f) IPR1;
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volatile __IPR1bits_t __at (0xf9f) IPR1bits;
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__sfr __at (0xfa0) PIE2;
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volatile __PIE2bits_t __at (0xfa0) PIE2bits;
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__sfr __at (0xfa1) PIR2;
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volatile __PIR2bits_t __at (0xfa1) PIR2bits;
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__sfr __at (0xfa2) IPR2;
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volatile __IPR2bits_t __at (0xfa2) IPR2bits;
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__sfr __at (0xfa6) EECON1;
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volatile __EECON1bits_t __at (0xfa6) EECON1bits;
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__sfr __at (0xfa7) EECON2;
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__sfr __at (0xfa8) EEDATA;
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__sfr __at (0xfa9) EEADR;
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__sfr __at (0xfab) RCSTA;
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volatile __RCSTAbits_t __at (0xfab) RCSTAbits;
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__sfr __at (0xfac) TXSTA;
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volatile __TXSTAbits_t __at (0xfac) TXSTAbits;
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__sfr __at (0xfad) TXREG;
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__sfr __at (0xfae) RCREG;
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__sfr __at (0xfaf) SPBRG;
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__sfr __at (0xfb1) T3CON;
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volatile __T3CONbits_t __at (0xfb1) T3CONbits;
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__sfr __at (0xfb2) TMR3L;
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__sfr __at (0xfb3) TMR3H;
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__sfr __at (0xfba) CCP2CON;
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volatile __CCP2CONbits_t __at (0xfba) CCP2CONbits;
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__sfr __at (0xfbb) CCPR2L;
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__sfr __at (0xfbc) CCPR2H;
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__sfr __at (0xfbd) CCP1CON;
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volatile __CCP1CONbits_t __at (0xfbd) CCP1CONbits;
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__sfr __at (0xfbe) CCPR1L;
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__sfr __at (0xfbf) CCPR1H;
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__sfr __at (0xfc1) ADCON1;
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volatile __ADCON1bits_t __at (0xfc1) ADCON1bits;
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__sfr __at (0xfc2) ADCON0;
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volatile __ADCON0bits_t __at (0xfc2) ADCON0bits;
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__sfr __at (0xfc3) ADRESL;
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__sfr __at (0xfc4) ADRESH;
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__sfr __at (0xfc5) SSPCON2;
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volatile __SSPCON2bits_t __at (0xfc5) SSPCON2bits;
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__sfr __at (0xfc6) SSPCON1;
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volatile __SSPCON1bits_t __at (0xfc6) SSPCON1bits;
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__sfr __at (0xfc7) SSPSTAT;
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volatile __SSPSTATbits_t __at (0xfc7) SSPSTATbits;
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__sfr __at (0xfc8) SSPADD;
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__sfr __at (0xfc9) SSPBUF;
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__sfr __at (0xfca) T2CON;
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volatile __T2CONbits_t __at (0xfca) T2CONbits;
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__sfr __at (0xfcb) PR2;
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__sfr __at (0xfcc) TMR2;
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__sfr __at (0xfcd) T1CON;
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volatile __T1CONbits_t __at (0xfcd) T1CONbits;
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__sfr __at (0xfce) TMR1L;
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__sfr __at (0xfcf) TMR1H;
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__sfr __at (0xfd0) RCON;
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volatile __RCONbits_t __at (0xfd0) RCONbits;
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__sfr __at (0xfd1) WDTCON;
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volatile __WDTCONbits_t __at (0xfd1) WDTCONbits;
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__sfr __at (0xfd2) LVDCON;
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volatile __LVDCONbits_t __at (0xfd2) LVDCONbits;
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__sfr __at (0xfd3) OSCCON;
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volatile __OSCCONbits_t __at (0xfd3) OSCCONbits;
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__sfr __at (0xfd5) T0CON;
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volatile __T0CONbits_t __at (0xfd5) T0CONbits;
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__sfr __at (0xfd6) TMR0L;
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__sfr __at (0xfd7) TMR0H;
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__sfr __at (0xfd8) STATUS;
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volatile __STATUSbits_t __at (0xfd8) STATUSbits;
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__sfr __at (0xfd9) FSR2L;
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__sfr __at (0xfda) FSR2H;
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__sfr __at (0xfdb) PLUSW2;
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__sfr __at (0xfdc) PREINC2;
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__sfr __at (0xfdd) POSTDEC2;
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__sfr __at (0xfde) POSTINC2;
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__sfr __at (0xfdf) INDF2;
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__sfr __at (0xfe0) BSR;
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__sfr __at (0xfe1) FSR0L;
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__sfr __at (0xfe2) FSR0H;
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__sfr __at (0xfe3) PLUSW0;
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__sfr __at (0xfe4) PREINC0;
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__sfr __at (0xfe5) POSTDEC0;
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__sfr __at (0xfe6) POSTINC0;
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__sfr __at (0xfe7) INDF0;
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__sfr __at (0xfe8) WREG;
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__sfr __at (0xfe9) FSR1L;
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__sfr __at (0xfea) FSR1H;
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__sfr __at (0xfeb) PLUSW1;
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__sfr __at (0xfec) PREINC1;
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__sfr __at (0xfed) POSTDEC1;
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__sfr __at (0xfee) POSTINC1;
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__sfr __at (0xfef) INDF1;
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__sfr __at (0xff0) INTCON3;
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volatile __INTCON3bits_t __at (0xff0) INTCON3bits;
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__sfr __at (0xff1) INTCON2;
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volatile __INTCON2bits_t __at (0xff1) INTCON2bits;
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__sfr __at (0xff2) INTCON;
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volatile __INTCONbits_t __at (0xff2) INTCONbits;
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__sfr __at (0xff3) PRODL;
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__sfr __at (0xff4) PRODH;
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__sfr __at (0xff5) TABLAT;
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__sfr __at (0xff6) TBLPTRL;
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__sfr __at (0xff7) TBLPTRH;
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__sfr __at (0xff8) TBLPTRU;
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__sfr __at (0xff9) PCL;
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__sfr __at (0xffa) PCLATH;
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__sfr __at (0xffb) PCLATU;
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__sfr __at (0xffc) STKPTR;
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volatile __STKPTRbits_t __at (0xffc) STKPTRbits;
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__sfr __at (0xffd) TOSL;
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__sfr __at (0xffe) TOSH;
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__sfr __at (0xfff) TOSU;
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