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1 tk 1
;
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; MIOS Shift Register IO Handler
3
;
4
; ==========================================================================
5
;
6
;  Copyright 1998-2006 Thorsten Klose (tk@midibox.org)
7
;  Licensed for personal non-commercial use only.
8
;  All other rights reserved.
9
;
10
; ==========================================================================
11
 
12
;; pins of SRIO shift registers
13
MIOS_SRIO_LAT_SCLK	EQU	LATD	; Pin D.3
14
MIOS_SRIO_PIN_SCLK	EQU	3
15
MIOS_SRIO_LAT_RCLK	EQU	LATD	; Pin D.2
16
MIOS_SRIO_PIN_RCLK	EQU	2
17
MIOS_SRIO_PORT_DIN	EQU	PORTD	; Pin D.1
18
MIOS_SRIO_PIN_DIN	EQU	1
19
MIOS_SRIO_LAT_DOUT	EQU	LATD	; Pin D.0
20
MIOS_SRIO_PIN_DOUT	EQU	0
21
 
22
;; Touch Sensor Pin D.4
23
MIOS_SRIO_LAT_TS	EQU	LATD
24
MIOS_SRIO_PIN_TS	EQU	4
25
 
26
 
27
;; --------------------------------------------------------------------------
28
;;  MIOS SRIO Tick
29
;; --------------------------------------------------------------------------
30
MIOS_SRIO_Tick
31
	movff	FSR0L, IRQ_TMP1			; store FSR0 in temp. register
32
	movff	FSR0H, IRQ_TMP2
33
 
34
	SET_BSR	MIOS_IRQ_TMP_CTR
35
 
36
	;; send a short pulse over port J14 of the core module for capacitive touch sensors
37
	movf	MIOS_SRIO_TS_SENSITIVITY, W, BANKED
38
	bnz	MIOS_SRIO_TS_Enabled
39
MIOS_SRIO_TS_Disabled
40
        bcf	MIOS_SRIO_LAT_RCLK, MIOS_SRIO_PIN_RCLK	; register button values
41
	clrf	MIOS_IRQ_TMP_CTR, BANKED		; init loop counter for register upload
42
	nop
43
	nop
44
	nop
45
        bsf     MIOS_SRIO_LAT_RCLK, MIOS_SRIO_PIN_RCLK	; release register clock
46
	rgoto	MIOS_SRIO_TS_Cont			; continue behind TS handler
47
 
48
MIOS_SRIO_TS_Enabled
49
	movwf	MIOS_IRQ_TMP_CTR, BANKED		; use sensitivity as loop counter
50
 
51
  	bsf	MIOS_SRIO_LAT_TS, MIOS_SRIO_PIN_TS	; touch sensor pin = 1
52
MIOS_SRIO_TS_Loop
53
	decfsz	MIOS_IRQ_TMP_CTR, F, BANKED
54
	rgoto	MIOS_SRIO_TS_Loop
55
        bcf	MIOS_SRIO_LAT_RCLK, MIOS_SRIO_PIN_RCLK	; register button values
56
	clrf	MIOS_IRQ_TMP_CTR, BANKED		; init loop counter for register upload
57
	nop
58
	nop
59
	nop
60
        bsf     MIOS_SRIO_LAT_RCLK, MIOS_SRIO_PIN_RCLK	; release register clock
61
	bcf	MIOS_SRIO_LAT_TS, MIOS_SRIO_PIN_TS	; touch sensor pin = 0
62
MIOS_SRIO_TS_Cont
63
 
64
	lfsr	FSR0, MIOS_SR_DIN_CHANGED_0
65
	lfsr	FSR1, MIOS_SR_DIN_0
66
	lfsr	FSR2, MIOS_SR_DOUT_0
67
	decf	MIOS_SRIO_NUMBER, W, BANKED
68
	addwf	FSR2L, F
69
 
70
	movf	MIOS_SRIO_NUMBER, W, BANKED
71
	movwf	MIOS_IRQ_TMP_CTR, BANKED
72
 
73
	;; feed the SRs
74
MIOS_SRIO_Loop
75
        btfsc   MIOS_SRIO_PORT_DIN, MIOS_SRIO_PIN_DIN
76
	bsf	IRQ_TMP5, 7
77
	bsf	MIOS_SRIO_LAT_DOUT, MIOS_SRIO_PIN_DOUT
78
	btfss	INDF2, 0
79
	bcf	MIOS_SRIO_LAT_DOUT, MIOS_SRIO_PIN_DOUT
80
        btfss   MIOS_SRIO_PORT_DIN, MIOS_SRIO_PIN_DIN
81
	bcf	IRQ_TMP5, 7
82
        bsf     MIOS_SRIO_LAT_SCLK, MIOS_SRIO_PIN_SCLK
83
	nop
84
 
85
        btfsc   MIOS_SRIO_PORT_DIN, MIOS_SRIO_PIN_DIN
86
	bsf	IRQ_TMP5, 6
87
        bcf     MIOS_SRIO_LAT_SCLK, MIOS_SRIO_PIN_SCLK
88
	bsf	MIOS_SRIO_LAT_DOUT, MIOS_SRIO_PIN_DOUT
89
	btfss	INDF2, 1
90
	bcf	MIOS_SRIO_LAT_DOUT, MIOS_SRIO_PIN_DOUT
91
        btfss   MIOS_SRIO_PORT_DIN, MIOS_SRIO_PIN_DIN
92
	bcf	IRQ_TMP5, 6
93
        bsf     MIOS_SRIO_LAT_SCLK, MIOS_SRIO_PIN_SCLK
94
	nop
95
 
96
        btfsc   MIOS_SRIO_PORT_DIN, MIOS_SRIO_PIN_DIN
97
	bsf	IRQ_TMP5, 5
98
        bcf     MIOS_SRIO_LAT_SCLK, MIOS_SRIO_PIN_SCLK
99
	bsf	MIOS_SRIO_LAT_DOUT, MIOS_SRIO_PIN_DOUT
100
	btfss	INDF2, 2
101
	bcf	MIOS_SRIO_LAT_DOUT, MIOS_SRIO_PIN_DOUT
102
        btfss   MIOS_SRIO_PORT_DIN, MIOS_SRIO_PIN_DIN
103
	bcf	IRQ_TMP5, 5
104
        bsf     MIOS_SRIO_LAT_SCLK, MIOS_SRIO_PIN_SCLK
105
	nop
106
 
107
        btfsc   MIOS_SRIO_PORT_DIN, MIOS_SRIO_PIN_DIN
108
	bsf	IRQ_TMP5, 4
109
        bcf     MIOS_SRIO_LAT_SCLK, MIOS_SRIO_PIN_SCLK
110
	bsf	MIOS_SRIO_LAT_DOUT, MIOS_SRIO_PIN_DOUT
111
	btfss	INDF2, 3
112
	bcf	MIOS_SRIO_LAT_DOUT, MIOS_SRIO_PIN_DOUT
113
        btfss   MIOS_SRIO_PORT_DIN, MIOS_SRIO_PIN_DIN
114
	bcf	IRQ_TMP5, 4
115
        bsf     MIOS_SRIO_LAT_SCLK, MIOS_SRIO_PIN_SCLK
116
	nop
117
 
118
        btfsc   MIOS_SRIO_PORT_DIN, MIOS_SRIO_PIN_DIN
119
	bsf	IRQ_TMP5, 3
120
        bcf     MIOS_SRIO_LAT_SCLK, MIOS_SRIO_PIN_SCLK
121
	bsf	MIOS_SRIO_LAT_DOUT, MIOS_SRIO_PIN_DOUT
122
	btfss	INDF2, 4
123
	bcf	MIOS_SRIO_LAT_DOUT, MIOS_SRIO_PIN_DOUT
124
        btfss   MIOS_SRIO_PORT_DIN, MIOS_SRIO_PIN_DIN
125
	bcf	IRQ_TMP5, 3
126
        bsf     MIOS_SRIO_LAT_SCLK, MIOS_SRIO_PIN_SCLK
127
	nop
128
 
129
        btfsc   MIOS_SRIO_PORT_DIN, MIOS_SRIO_PIN_DIN
130
	bsf	IRQ_TMP5, 2
131
        bcf     MIOS_SRIO_LAT_SCLK, MIOS_SRIO_PIN_SCLK
132
	bsf	MIOS_SRIO_LAT_DOUT, MIOS_SRIO_PIN_DOUT
133
	btfss	INDF2, 5
134
	bcf	MIOS_SRIO_LAT_DOUT, MIOS_SRIO_PIN_DOUT
135
        btfss   MIOS_SRIO_PORT_DIN, MIOS_SRIO_PIN_DIN
136
	bcf	IRQ_TMP5, 2
137
        bsf     MIOS_SRIO_LAT_SCLK, MIOS_SRIO_PIN_SCLK
138
	nop
139
 
140
        btfsc   MIOS_SRIO_PORT_DIN, MIOS_SRIO_PIN_DIN
141
	bsf	IRQ_TMP5, 1
142
        bcf     MIOS_SRIO_LAT_SCLK, MIOS_SRIO_PIN_SCLK
143
	bsf	MIOS_SRIO_LAT_DOUT, MIOS_SRIO_PIN_DOUT
144
	btfss	INDF2, 6
145
	bcf	MIOS_SRIO_LAT_DOUT, MIOS_SRIO_PIN_DOUT
146
        btfss   MIOS_SRIO_PORT_DIN, MIOS_SRIO_PIN_DIN
147
	bcf	IRQ_TMP5, 1
148
        bsf     MIOS_SRIO_LAT_SCLK, MIOS_SRIO_PIN_SCLK
149
	nop
150
 
151
        btfsc   MIOS_SRIO_PORT_DIN, MIOS_SRIO_PIN_DIN
152
	bsf	IRQ_TMP5, 0
153
        bcf     MIOS_SRIO_LAT_SCLK, MIOS_SRIO_PIN_SCLK
154
	bsf	MIOS_SRIO_LAT_DOUT, MIOS_SRIO_PIN_DOUT
155
	btfss	INDF2, 7
156
	bcf	MIOS_SRIO_LAT_DOUT, MIOS_SRIO_PIN_DOUT
157
        btfss   MIOS_SRIO_PORT_DIN, MIOS_SRIO_PIN_DIN
158
	bcf	IRQ_TMP5, 0
159
        bsf     MIOS_SRIO_LAT_SCLK, MIOS_SRIO_PIN_SCLK
160
	nop
161
 
162
	movf	IRQ_TMP5, W
163
	xorwf	INDF1, W
164
	iorwf	POSTINC0, F
165
 
166
        bcf     MIOS_SRIO_LAT_SCLK, MIOS_SRIO_PIN_SCLK
167
 
168
	movf	IRQ_TMP5, W
169
	movwf	POSTINC1
170
 
171
	movf	POSTDEC2, W
172
MIOS_SRIO_Loop_Next
173
	decfsz	MIOS_IRQ_TMP_CTR, F, BANKED
174
	rgoto	MIOS_SRIO_Loop
175
 
176
        bcf     MIOS_SRIO_LAT_RCLK, MIOS_SRIO_PIN_RCLK	; latch LED values
177
 
178
	movff	IRQ_TMP1, FSR0L				; restore FSR0 from temp. register
179
	movff	IRQ_TMP2, FSR0H				; (should be executed here to stretch the RCLK pulse)
180
 
181
        bsf     MIOS_SRIO_LAT_RCLK, MIOS_SRIO_PIN_RCLK	; latch LED values
182
 
183
	bsf	MIOS_SRIO_LAT_DOUT, MIOS_SRIO_PIN_DOUT	; set SR OUT pin to defined value
184
 
185
	return
186
 
187
;; --------------------------------------------------------------------------
188
;;  FUNCTION: MIOS_SRIO_NumberSet
189
;;  C_DECLARATION: void MIOS_SRIO_NumberSet(unsigned char number_sr)
190
;;  DESCRIPTION: sets number of available SR registers
191
;;  If number > 16, value will be forced to 16
192
;;  IN:	  number of SRs in WREG
193
;;  C_IN:  number of SRs in <number_sr>
194
;;  OUT:  -
195
;;  C_OUT:  -
196
;;  USES: BSR
197
;; --------------------------------------------------------------------------
198
MIOS_SRIO_NumberSet
199
	SET_BSR	MIOS_SRIO_NUMBER
200
	movwf	MIOS_SRIO_NUMBER, BANKED
201
	andlw	0xf0
202
	skpnz
203
	return
204
	movlw	0x10
205
	movwf	MIOS_SRIO_NUMBER, BANKED
206
	return
207
 
208
;; --------------------------------------------------------------------------
209
;;  FUNCTION: MIOS_SRIO_NumberGet
210
;;  C_DECLARATION: unsigned char MIOS_SRIO_NumberGet(void)
211
;;  DESCRIPTION: returns number of available SR registers
212
;;  IN:	  -
213
;;  C_IN:  -
214
;;  OUT:  number of SRs in MIOS_PARAMETER1 and WREG
215
;;  C_OUT: number of SRs
216
;;  USES: BSR
217
;; --------------------------------------------------------------------------
218
MIOS_SRIO_NumberGet
219
	SET_BSR	MIOS_SRIO_NUMBER
220
	movf	MIOS_SRIO_NUMBER, W, BANKED
221
	movwf	MIOS_PARAMETER1
222
	return
223
 
224
 
225
;; --------------------------------------------------------------------------
226
;;  FUNCTION: MIOS_SRIO_UpdateFrqSet
227
;;  C_DECLARATION: void MIOS_SRIO_UpdateFrqSet(unsigned char update_frq)
228
;;  DESCRIPTION: sets the update frequency of SR registers
229
;;  IN:	  update frequency (unit: milliseconds) in WREG
230
;;  C_IN: update frequency (unit: milliseconds) in <update_frq>
231
;;  OUT:  -
232
;;  C_OUT:  -
233
;;  USES: BSR
234
;; --------------------------------------------------------------------------
235
MIOS_SRIO_UpdateFrqSet
236
	SET_BSR	MIOS_SRIO_UPDATE_FRQ
237
	movwf	MIOS_SRIO_UPDATE_FRQ, BANKED
238
	movf	MIOS_SRIO_UPDATE_FRQ, W, BANKED
239
	skpnz
240
	incf	MIOS_SRIO_UPDATE_FRQ, F, BANKED
241
	return
242
 
243
;; --------------------------------------------------------------------------
244
;;  FUNCTION: MIOS_SRIO_UpdateFrqGet
245
;;  C_DECLARATION: unsigned char MIOS_SRIO_UpdateFrqGet(void)
246
;;  DESCRIPTION: returns the update frequency of SR registers
247
;;  IN:	  -
248
;;  C_IN:  -
249
;;  OUT:  update frequency (unit: milliseconds) in MIOS_PARAMETER1 and WREG
250
;;  C_OUT: update frequency (unit: milliseconds)
251
;;  USES: BSR
252
;; --------------------------------------------------------------------------
253
MIOS_SRIO_UpdateFrqGet
254
	SET_BSR	MIOS_SRIO_UPDATE_FRQ
255
	movf	MIOS_SRIO_UPDATE_FRQ, W, BANKED
256
	movwf	MIOS_PARAMETER1
257
	return
258
 
259
 
260
;; --------------------------------------------------------------------------
261
;;  FUNCTION: MIOS_SRIO_TS_SensitivitySet
262
;;  C_DECLARATION: void MIOS_SRIO_TS_SensitivitySet(unsigned char sensitivity)
263
;;  DESCRIPTION: sets the touch sensor sensitivity.<BR>
264
;;  sensitivity == 0x00 disables the TS so that Pin RD.4 (J14 of the core module)
265
;;  won't be driven by MIOS anymore and therefore is free for other purposes
266
;;  IN:	  sensitivity value in WREG
267
;;  C_IN: sensitivity value in <sensitivity>
268
;;  OUT:  -
269
;;  C_OUT:  -
270
;;  USES: BSR
271
;; --------------------------------------------------------------------------
272
MIOS_SRIO_TS_SensitivitySet
273
	SET_BSR	MIOS_SRIO_TS_SENSITIVITY
274
	movwf	MIOS_SRIO_TS_SENSITIVITY, BANKED
275
	return
276
 
277
;; --------------------------------------------------------------------------
278
;;  FUNCTION: MIOS_SRIO_TS_SensitivityGet
279
;;  C_DECLARATION: unsigned char MIOS_SRIO_TS_SensitivityGet(void)
280
;;  DESCRIPTION: returns the touchsensor sensitivity
281
;;  IN:	  -
282
;;  C_IN:  -
283
;;  OUT:  sensitivity value in MIOS_PARAMETER1 and WREG
284
;;  C_OUT:  sensitivity value
285
;;  USES: BSR
286
;; --------------------------------------------------------------------------
287
MIOS_SRIO_TS_SensitivityGet
288
	SET_BSR	MIOS_SRIO_TS_SENSITIVITY
289
	movf	MIOS_SRIO_TS_SENSITIVITY, W, BANKED
290
	movwf	MIOS_PARAMETER1
291
	return
292
 
293
;; --------------------------------------------------------------------------
294
;;  FUNCTION: MIOS_SRIO_DebounceSet
295
;;  C_DECLARATION: void MIOS_SRIO_DebounceSet(unsigned char debounce_value)
296
;;  DESCRIPTION: sets the debounce counter reload value for the DIN SR registers
297
;;  which are not assigned to rotary encoders to debounce low-quality buttons.<BR><BR>
298
;;
299
;;  Debouncing is realized in the following way: on every button movement the
300
;;  debounce preload value will be loaded into the debounce counter register.
301
;;  The counter will be decremented on every SRIO update cycle. So long as this
302
;;  counter isn't zero, button changes will still be recorded, but they won't trigger
303
;;  the USER_DIN_NotifyToggle function.<BR><BR>
304
;;
305
;;  No (intended) button movement will get lost, but the latency will be
306
;;  increased. Example: if the update frequency is set to 1 mS, and the
307
;;  debounce value to 32, the first button movement will be regognized with
308
;;  a worst-case latency of 1 mS. Every additional button movement which happens
309
;;  within 32 mS will be regognized within a worst-case latency of 32 mS.
310
;;  After the debounce time has passed, the worst-case latency is 1 mS again.<BR><BR>
311
;;
312
;;  Note that in MIOS versions below v1.9c, the debounce counter also affected
313
;;  the rotary encoders and DOUT registers (they where not serviced).<BR>
314
;;  With MIOS V1.9c and higher, this problem doesn't exist anymore and the
315
;;  debouncing feature can be used in nearly all applications.<BR>
316
;;  Only exception: if the application should record pin changes from digital
317
;;  sensors which are switching very fast, then debouncing should be ommited.
318
;;
319
;;  IN:	  debounce counter reload value in WREG
320
;;  C_IN: debounce counter reload value in <debounce_value>
321
;;  OUT:  -
322
;;  C_OUT:  -
323
;;  USES: BSR
324
;; --------------------------------------------------------------------------
325
MIOS_SRIO_DebounceSet
326
	SET_BSR	MIOS_SRIO_DEBOUNCE
327
	movwf	MIOS_SRIO_DEBOUNCE, BANKED
328
	return
329
 
330
;; --------------------------------------------------------------------------
331
;;  FUNCTION: MIOS_SRIO_DebounceGet
332
;;  C_DECLARATION: unsigned char MIOS_SRIO_DebounceGet(void)
333
;;  DESCRIPTION: returns the debounce counter reload value of the DIN SR registers
334
;;  IN:	  -
335
;;  C_IN:  -
336
;;  OUT:  debounce counter reload value in WREG and MIOS_PARAMETER1
337
;;  C_OUT:  debounce counter reload value
338
;;  USES: BSR
339
;; --------------------------------------------------------------------------
340
MIOS_SRIO_DebounceGet
341
	SET_BSR	MIOS_SRIO_DEBOUNCE
342
	movf	MIOS_SRIO_DEBOUNCE, W, BANKED
343
	movwf	MIOS_PARAMETER1
344
	return
345
 
346
 
347
 
348
;; --------------------------------------------------------------------------
349
;;  INTERNAL
350
;;  MIOS SRIO Get: returns value from a DIN/DOUT register
351
;;  IN:	  Pin number in WREG, register address in FSR0
352
;;  OUT:  1 if pin is +5V, 0 if pin is 0V in MIOS_PARAMETER1 and WREG
353
;;  USES: FSR1 and BSR
354
;; --------------------------------------------------------------------------
355
MIOS_SRIO_Get
356
	movwf	MIOS_PARAMETER1
357
 
358
	rlf	WREG, F
359
	swapf	WREG, W
360
	andlw	0x0f
361
	addwf	FSR1L, F
362
 
363
	movf	MIOS_PARAMETER1, W
364
	andlw	0x07
365
	call	MIOS_HLP_GetBitORMask
366
	andwf	INDF1, W
367
	movlw	0x00
368
	skpz
369
	movlw	0x01
370
	andlw	0x01					; for correct status (Z flag set/not set...)
371
	movwf	MIOS_PARAMETER1
372
	return
373
 
374
;; --------------------------------------------------------------------------
375
;;  INTERNAL
376
;;  MIOS SRIO Get2: returns value from two DIN/DOUT Neighbour Pins
377
;;  IN:	  number of first Pin in WREG, register address in FSR
378
;;  OUT:  0, 1, 2, 3 in MIOS_PARAMETER1 and WREG
379
;;  USES: FSR1 and BSR
380
;; --------------------------------------------------------------------------
381
MIOS_SRIO_Get2
382
	movwf	MIOS_PARAMETER1
383
 
384
	rlf	WREG, F
385
	swapf	WREG, W
386
	andlw	0x0f
387
	addwf	FSR1L, F
388
 
389
	BRA_IFSET MIOS_PARAMETER1, 2, ACCESS, MIOS_SRIO_Get2_Cont_Pin4567
390
MIOS_SRIO_Get2_Cont_Pin0123
391
	BRA_IFSET MIOS_PARAMETER1, 1, ACCESS, MIOS_SRIO_Get2_Cont_Pin23
392
MIOS_SRIO_Get2_Cont_Pin01
393
	movlw	0x00
394
	btfsc	INDF1, 0
395
	iorlw	0x01
396
	btfsc	INDF1, 1
397
	iorlw	0x02
398
	rgoto	MIOS_SRIO_Get2_End
399
 
400
MIOS_SRIO_Get2_Cont_Pin23
401
	movlw	0x00
402
	btfsc	INDF1, 2
403
	iorlw	0x01
404
	btfsc	INDF1, 3
405
	iorlw	0x02
406
	rgoto	MIOS_SRIO_Get2_End
407
 
408
MIOS_SRIO_Get2_Cont_Pin4567
409
	BRA_IFSET MIOS_PARAMETER1, 1, ACCESS, MIOS_SRIO_Get2_Cont_Pin67
410
MIOS_SRIO_Get2_Cont_Pin45
411
	movlw	0x00
412
	btfsc	INDF1, 4
413
	iorlw	0x01
414
	btfsc	INDF1, 5
415
	iorlw	0x02
416
	rgoto	MIOS_SRIO_Get2_End
417
 
418
MIOS_SRIO_Get2_Cont_Pin67
419
	movlw	0x00
420
	btfsc	INDF1, 6
421
	iorlw	0x01
422
	btfsc	INDF1, 7
423
	iorlw	0x02
424
	;; 	rgoto	MIOS_SRIO_Get2_End
425
 
426
MIOS_SRIO_Get2_End
427
	andlw	0x03					; for correct status (Z flag set/not set...)
428
	movwf	MIOS_PARAMETER1
429
	return
430
 
431
;; --------------------------------------------------------------------------
432
;;  INTERNAL
433
;;  MIOS SRIO Set0: sets DIN/DOUT/CHANGED register flag to 0
434
;;  IN:	  Pin number in WREG, register address in FSR0
435
;;  OUT:  -
436
;;  USES: FSR1 and BSR
437
;; --------------------------------------------------------------------------
438
MIOS_SRIO_Set0
439
	movwf	MIOS_PARAMETER1
440
 
441
	rlf	WREG, F
442
	swapf	WREG, W
443
	andlw	0x0f
444
	addwf	FSR1L, F
445
 
446
	movf	MIOS_PARAMETER1, W
447
	andlw	0x07
448
	call	MIOS_HLP_GetBitANDMask
449
	andwf	INDF1, F
450
	return
451
 
452
;; --------------------------------------------------------------------------
453
;;  INTERNAL
454
;;  MIOS SRIO Set0: sets DIN/DOUT register flag to 0
455
;;  IN:	  Pin number in WREG, register address in FSR0
456
;;  OUT:  -
457
;;  USES: FSR1 and BSR
458
;; --------------------------------------------------------------------------
459
MIOS_SRIO_Set1
460
	movwf	MIOS_PARAMETER1
461
 
462
	rlf	WREG, F
463
	swapf	WREG, W
464
	andlw	0x0f
465
	addwf	FSR1L, F
466
 
467
	movf	MIOS_PARAMETER1, W
468
	andlw	0x07
469
	call	MIOS_HLP_GetBitORMask
470
	iorwf	INDF1, F
471
	return
472
 
473
;; --------------------------------------------------------------------------
474
;;  INTERNAL
475
;;  MIOS SRIO Set00: clears two neighboured DIN/DOUT/CHANGED register flags
476
;;  IN:	  Number of first pin in WREG, register address in FSR0
477
;;  OUT:  -
478
;;  USES: FSR1 and BSR
479
;; --------------------------------------------------------------------------
480
MIOS_SRIO_Set00
481
	movwf	MIOS_PARAMETER1
482
 
483
	rlf	WREG, F
484
	swapf	WREG, W
485
	andlw	0x0f
486
	addwf	FSR1L, F
487
 
488
	BRA_IFSET MIOS_PARAMETER1, 2, ACCESS, MIOS_SRIO_Set00_Cont_Pin4567
489
MIOS_SRIO_Set00_Cont_Pin0123
490
	BRA_IFSET MIOS_PARAMETER1, 1, ACCESS, MIOS_SRIO_Set00_Cont_Pin23
491
MIOS_SRIO_Set00_Cont_Pin01
492
	movlw	0xfc
493
	rgoto	MIOS_SRIO_Set00_End
494
 
495
MIOS_SRIO_Set00_Cont_Pin23
496
	movlw	0xf3
497
	rgoto	MIOS_SRIO_Set00_End
498
 
499
MIOS_SRIO_Set00_Cont_Pin4567
500
	BRA_IFSET MIOS_PARAMETER1, 1, ACCESS, MIOS_SRIO_Set00_Cont_Pin67
501
MIOS_SRIO_Set00_Cont_Pin45
502
	movlw	0xcf
503
	rgoto	MIOS_SRIO_Set00_End
504
 
505
MIOS_SRIO_Set00_Cont_Pin67
506
	movlw	0x3f
507
	;; 	rgoto	MIOS_SRIO_Set00_End
508
 
509
MIOS_SRIO_Set00_End
510
	andwf	INDF1, F
511
	return