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53 tk 1
; $Id: mios_flash.inc 53 2008-01-30 22:52:41Z tk $
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;
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; MIOS FLASH routines
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;
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; ==========================================================================
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;
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;  Copyright 1998-2006 Thorsten Klose (tk@midibox.org)
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;  Licensed for personal non-commercial use only.
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;  All other rights reserved.
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;
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; ==========================================================================
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;; --------------------------------------------------------------------------
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;;  FUNCTION: MIOS_FLASH_Write
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;;  C_DECLARATION: unsigned char MIOS_FLASH_Write(code char *addr, char *buffer)
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;;  DESCRIPTION: writes 64 bytes into FLASH memory<BR>
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;;  Write access will be skipped if content is equal to the bytes in the
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;;  buffer. Writes to MIOS prgram space will be prevented:<BR>
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;;  PIC18F452:  0x0000-0x2fff not writable
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;;  PIC18F4620:	0x0000-0x2fff not writable
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;;  Returned Error Status:<BR>
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;;     0x00: no error<BR>
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;;     0x01: byte mismatch (write failed)<BR>
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;;     0x02: access error (memory protected)
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;;  IN:	  pointer to write buffer (64 bytes) in FSR1
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;;        flash address in TBLPRT_[LH] (must be aligned to 64 byte page)
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;;  C_IN: pointer to write buffer (64 bytes) in <buffer>
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;;        flash address in <addr> (must be aligned to 64 byte page)
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;;  OUT:  error status in WREG and MIOS_PARAMETER1
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;;        TBLPTR will be incremented to next page address (+64)
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;;	  FSR1 will be left untouched
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;;  C_OUT: returns error status
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;;  USES: BSR, TBLPTR[LH], TABLAT, EECON1, EECON2
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;;  EXAMPLE:
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;;
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;;	;; write a page of 64 bytes to flash memory at address 0x7000
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;;	TABLE_ADDR 0x7000		; load address into TABLPTR[LH]
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;;	lfsr	FSR1, 0x100		; a free 64 byte buffer in RAM which
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;;                                      ; contains some data
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;;	call	MIOS_FLASH_Write	; initiate the write
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;;	bnz	FlashProgrammingFailed	; branch to your exception handler
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;;                                      ; if necessary
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;;
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;;  C_EXAMPLE:
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;;
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;;	unsigned char buffer[64];
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;;	unsigned char i;
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;;
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;;	// fill buffer with some bytes
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;;	for(i=0; i<64; ++i)
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;;	  buffer[i] = i;
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;;
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;;	// write a page of 64 bytes to flash memory at address 0x7000
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;;	if( MIOS_FLASH_Write(0x7000, buffer) ) {
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;;	  // error handler
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;;	}
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;;
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;; --------------------------------------------------------------------------
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MIOS_FLASH_Write
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	SET_BSR	MIOS_TMP1
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	;; align TBLPTRL
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	movlw	0xc0
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	andwf	TBLPTRL, F
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	;; prevent writes to addresses > PIC code size
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	;; we calculate with 4k blocks, accordingly we have to compare it against TBLPTRU[3:0]:TBLPTRH[7:4]
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	swapf	TBLPTRU, W
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	andlw	0xf0
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	movwf	MIOS_TMP1, BANKED
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	swapf	TBLPTRH, W
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	andlw	0x0f
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	iorwf	MIOS_TMP1, F, BANKED
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	movlw	(PIC_DERIVATIVE_CODE_SIZE >> 12) & 0xff
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	cpfslt	MIOS_TMP1, BANKED
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	rgoto MIOS_FLASH_Write_AccessError
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	;; prevent writes to addresses < 0x3000
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#if PIC_DERIVATIVE_CODE_SIZE > 0x10000
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	movf	TBLPTRU, W
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	bnz	MIOS_FLASH_Write_AccessOk
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#endif
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	movlw	0x2f
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	cpfsgt	TBLPTRH, ACCESS
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	rgoto MIOS_FLASH_Write_AccessError
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MIOS_FLASH_Write_AccessOk
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	;; first compare buffer with Flash content
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	clrf	MIOS_TMP1, BANKED
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MIOS_FLASH_Write_CompareLoop1
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	tblrd*+
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	movf	MIOS_TMP1, W, BANKED
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	movf	PLUSW1, W
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	xorwf	TABLAT, W
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	bnz	MIOS_FLASH_Write_CompareMismatch
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	incf	MIOS_TMP1, F, BANKED
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	BRA_IFCLR MIOS_TMP1, 6, BANKED, MIOS_FLASH_Write_CompareLoop1
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	;; no mismatches: don't write, error status = ok
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	movlw	0x00
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	rgoto	MIOS_FLASH_Write_End
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MIOS_FLASH_Write_CompareMismatch
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	tblrd*-				; fix table pointer
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	movlw	0xc0
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	andwf	TBLPTRL, F
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	;; all interrupts have to be disabled during write
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	;; see PIC18F452 B2 silicon errata
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	IRQ_DISABLE			; as IRQs are disabled here, we can use the IRQ tmp registers for
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	movff	PIE1, IRQ_TMP1		; saving the control registers :)
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	movff	PIE2, IRQ_TMP2
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	movff	INTCON, IRQ_TMP3
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	movff	INTCON2, IRQ_TMP4
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	movff	INTCON3, IRQ_TMP5
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	clrf	PIE1
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	clrf	PIE2
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	clrf	INTCON
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	clrf	INTCON2
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	clrf	INTCON3
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MIOS_FLASH_Write_ErasePage
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	bsf	EECON1, EEPGD		; point to FLASH program memory
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	bcf	EECON1, CFGS		; access FLASH program memory
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	bsf	EECON1, WREN		; enable write to memory
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	bsf	EECON1, FREE		; enable Row Erase operation
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	movlw	0x55			; write 55h
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	movwf	EECON2
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	movlw	0xaa			; write AAh
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	movwf	EECON2
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	bsf	EECON1, WR		; start erase (CPU stall)
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	tblrd*-				; dummy read decrement
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MIOS_FLASH_WritePage
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	clrf	MIOS_TMP1, BANKED	; 8 * 8 bytes row to write
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MIOS_FLASH_WritePageLoop
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MIOS_FLASH_WritePage_ToHRegs
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	movf	MIOS_TMP1, W, BANKED
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	movff	PLUSW1, TABLAT		; transfer byte into table latch
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	tblwt+*				; write data, perform a short write
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	incf	MIOS_TMP1, F, BANKED; loop until buffers are full
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	movf	MIOS_TMP1, W, BANKED
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	andlw	0x07
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	bnz	MIOS_FLASH_WritePage_ToHRegs
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MIOS_FLASH_ProgramMemory
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	bsf	EECON1, EEPGD		; point to FLASH program memory
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	bcf	EECON1, CFGS		; access FLASH program memory
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	bsf	EECON1, WREN		; enable write to memory
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	movlw	0x55			; write 55h
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	movwf	EECON2
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	movlw	0xaa			; write AAh
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	movwf	EECON2
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	bsf	EECON1, WR		; start program (CPU stall)
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	BRA_IFCLR MIOS_TMP1, 6, BANKED, MIOS_FLASH_WritePageLoop
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	bcf	EECON1, WREN		; disable write to memory
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	movff	IRQ_TMP1, PIE1		; restore IRQ control registers
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	movff	IRQ_TMP2, PIE2
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	movff	IRQ_TMP3, INTCON
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	movff	IRQ_TMP4, INTCON2
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	movff	IRQ_TMP5, INTCON3
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	IRQ_ENABLE
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	movlw	0xc0			; fix table pointer
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	andwf	TBLPTRL, F
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	;; compare buffer with Flash content - should be the same now!
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	clrf	MIOS_TMP1, BANKED
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MIOS_FLASH_Write_CompareLoop2
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	tblrd*+
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	movf	MIOS_TMP1, W, BANKED
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	movf	PLUSW1, W
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	xorwf	TABLAT, W
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 	bnz	MIOS_FLASH_Write_Error
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	incf	MIOS_TMP1, F, BANKED
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	BRA_IFCLR MIOS_TMP1, 6, BANKED, MIOS_FLASH_Write_CompareLoop2
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	movlw	0x00				; error status = OK
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	rgoto	MIOS_FLASH_Write_End
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MIOS_FLASH_Write_AccessError
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	movlw	0x02
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	rgoto	MIOS_FLASH_Write_End
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MIOS_FLASH_Write_Error
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	movlw	0x01				; error status = failed
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	;; 	rgoto	MIOS_FLASH_Write_End
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MIOS_FLASH_Write_End
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	movwf	MIOS_PARAMETER1
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	andlw	0xff				; update STATUS register
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	return
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;; --------------------------------------------------------------------------
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;;  FUNCTION: MIOS_FLASH_Read
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;;  C_DECLARATION: unsigned char MIOS_FLASH_Read(code char *addr, char *buffer)
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;;  DESCRIPTION: copies 64 bytes from FLASH memory to buffer
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;;  IN:	  pointer to read buffer (64 bytes) in FSR1
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;;        flash address in TBLPRT_[LH] (0x0000-0x7fc0, must be aligned to 64 byte page)
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;;  C_IN: pointer to read buffer (64 bytes) in <buffer>
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;;        flash address in <addr> (0x0000-0x7fc0, must be aligned to 64 byte page)
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;;  OUT:  memory dump in read buffer
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;;        TBLPTR will be incremented to next page address
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;;        FSR1 will be left untouched
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;;  C_OUT:  memory dump in <buffer>
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;;  USES: BSR, TBLPTR[LH], TABLAT
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;;  EXAMPLE:
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;;
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;;	;; read a page of 64 bytes from flash memory at address 0x7000
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;;	TABLE_ADDR 0x7000		; load address into TABLPTR[LH]
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;;	lfsr	FSR1, 0x100		; a free 64 byte buffer in RAM
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;;	call	MIOS_FLASH_Read		; initiate the read
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;;	;; flash dump now in buffer from 0x100-0x13f
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;;
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;;  C_EXAMPLE:
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;;
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;;	unsigned char buffer[64];
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;;
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;;	// read a page of 64 bytes from flash memory at address 0x7000
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;;	MIOS_FLASH_Read(0x7000, buffer);
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;;
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;; --------------------------------------------------------------------------
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MIOS_FLASH_Read
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	;; align TBLPTRL
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	movlw	0xc0
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	andwf	TBLPTRL, F
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	SET_BSR	MIOS_TMP1
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	clrf	MIOS_TMP1, BANKED
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MIOS_FLASH_ReadLoop
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	tblrd*+
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	movf	MIOS_TMP1, W, BANKED
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	movff	TABLAT, PLUSW1
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	incf	MIOS_TMP1, F, BANKED
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	BRA_IFCLR MIOS_TMP1, 6, BANKED, MIOS_FLASH_ReadLoop
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	return
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