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44 tk 1
; $Id: sid_sr.inc 44 2008-01-30 21:39:30Z tk $
1 tk 2
;
3
; MIDIbox SID
4
; SID Shift Register Service Routine
5
;
6
; ==========================================================================
7
;
8
;  Copyright 1998-2007 Thorsten Klose (tk@midibox.org)
9
;  Idea for Oscillator Phase Offset approach by Wilba
10
;  Licensed for personal non-commercial use only.
11
;  All other rights reserved.
12
;
13
; ==========================================================================
14
;
15
; define the pins to which the MBHPS_SID module is connected
16
;
17
SID_SR_LAT_SCLK	EQU	LATD
18
SID_SR_PIN_SCLK	EQU	5		; Pin D.5
19
SID_SR_LAT_RCLK	EQU	LATC
20
SID_SR_PIN_RCLK	EQU	4		; Pin C.4
21
SID_SR_LAT_OUT	EQU	LATD
22
SID_SR_PIN_OUT	EQU	6		; Pin D.6
23
 
24
SID_SR_LAT_WR	EQU	LATC
25
SID_SR_PIN_WR	EQU	5		; Pin C.5
26
SID_SR_LAT_WR2	EQU	LATD
27
SID_SR_PIN_WR2	EQU	4		; Pin D.4
28
 
29
 
30
;; --------------------------------------------------------------------------
31
;;  Initialize the MBHP_SID module
32
;; --------------------------------------------------------------------------
33
SID_SR_Init
34
	;; reset the SIDs
35
	lfsr	FSR0, SIDL_SHADOW_BASE
36
	lfsr	FSR1, SIDR_SHADOW_BASE
37
	clrf	MIOS_PARAMETER1
38
	movlw	0x00
39
	rcall	SID_SR_TransferL
40
	rgoto	SID_SR_TransferR
41
	;; reset will be released with first call of SID_SR_Handler
42
 
43
;; --------------------------------------------------------------------------
44
;;  Call this function to force an refresh of all SID registers
45
;; --------------------------------------------------------------------------
46
SID_SR_Refresh
47
	IRQ_DISABLE				; disable interrupts to avoid inconsistencies
48
 
49
	;; just modify the shadow registers, so that the content is not equal to the main register set
50
#if ENABLE_SWINSID
51
	movlw	0x20				; number of registers: 0x20
52
#else
53
	movlw	SIDx_MODE_VOL+1			; number of registers (0x19)
54
#endif
55
	movwf	TMP1				; TMP1 is the loop counter
56
	lfsr	FSR0, SIDL_BASE-1		; base address of SIDL registers
57
	lfsr	FSR1, SIDR_BASE-1		; base address of SIDR registers
58
SID_SR_Refresh_Loop
59
	incf	PREINC0, W
60
	movwf	PRODL
61
	movlw	LOW(SIDL_SHADOW_BASE-SIDL_BASE)
62
	movff	PRODL, PLUSW0
63
 
64
	incf	PREINC1, W
65
	movwf	PRODL
66
	movlw	LOW(SIDR_SHADOW_BASE-SIDR_BASE)
67
	movff	PRODL, PLUSW1
68
 
69
	decfsz	TMP1, F
70
	rgoto	SID_SR_Refresh_Loop
71
 
72
	;; set test flags for proper oscillator synchronisation
73
	SET_BSR	SIDL_BASE
74
	bsf	SIDL_BASE + SIDx_V1_CTRL, 3, BANKED
75
	bsf	SIDL_BASE + SIDx_V2_CTRL, 3, BANKED
76
	bsf	SIDL_BASE + SIDx_V3_CTRL, 3, BANKED
77
	bsf	SIDR_BASE + SIDx_V1_CTRL, 3, BANKED
78
	bsf	SIDR_BASE + SIDx_V2_CTRL, 3, BANKED
79
	bsf	SIDR_BASE + SIDx_V3_CTRL, 3, BANKED
80
 
81
	;; call transfer routine
82
	rcall	_SID_SR_Handler
83
 
84
	;; clear test flag and update again
85
	SET_BSR	SIDL_BASE
86
	bcf	SIDL_BASE + SIDx_V1_CTRL, 3, BANKED
87
	bcf	SIDL_BASE + SIDx_V2_CTRL, 3, BANKED
88
	bcf	SIDL_BASE + SIDx_V3_CTRL, 3, BANKED
89
	bcf	SIDR_BASE + SIDx_V1_CTRL, 3, BANKED
90
	bcf	SIDR_BASE + SIDx_V2_CTRL, 3, BANKED
91
	bcf	SIDR_BASE + SIDx_V3_CTRL, 3, BANKED
92
 
93
	rgoto	_SID_SR_Handler
94
 
95
 
96
;; --------------------------------------------------------------------------
97
;;  Check for changes in SID registers, transfer values to SID
98
;; --------------------------------------------------------------------------
99
SID_SR_Handler
100
	btfsc	SID_STAT, SID_STAT_ENGINE_DISABLE
101
	return
102
 
103
_SID_SR_Handler
104
	;; superfast unrolled loop with direct register accesses for best performance
105
	;; note that the control registers (which contain the gate flag) are not written
106
	;; before the other OSC registers have been initialized
107
 
108
SID_SR_HANDLER_MACRO MACRO reg
109
	LOCAL	SID_SR_HANDLER_MACRO_NEqu
110
	LOCAL	SID_SR_HANDLER_MACRO_End
111
 
112
	movf	SIDL_BASE + reg, W, BANKED	; branch if SIDL and SIDR register not equal
113
	cpfseq	SIDR_BASE + reg, BANKED
114
	rgoto	SID_SR_HANDLER_MACRO_NEqu
115
	movf	SIDL_SHADOW_BASE + reg, W, BANKED
116
	cpfseq	SIDR_SHADOW_BASE + reg, BANKED
117
	rgoto	SID_SR_HANDLER_MACRO_NEqu
118
 
119
	movf	SIDL_BASE + reg, W, BANKED	; transfer value to both SIDs if it has been changed
120
	cpfseq	SIDL_SHADOW_BASE + reg, BANKED
121
	rcall	SID_SR_TransferB
122
 
123
	rgoto	SID_SR_HANDLER_MACRO_End
124
 
125
SID_SR_HANDLER_MACRO_NEqu
126
	movf	SIDL_BASE + reg, W, BANKED	; transfer SIDL value if changed
127
	cpfseq	SIDL_SHADOW_BASE + reg, BANKED
128
	rcall	SID_SR_TransferL
129
 
130
	movf	SIDR_BASE + reg, W, BANKED	; transfer SIDR value if changed
131
	cpfseq	SIDR_SHADOW_BASE + reg, BANKED
132
	rcall	SID_SR_TransferR
133
 
134
SID_SR_HANDLER_MACRO_End
135
	incf	MIOS_PARAMETER1, F
136
	ENDM
137
 
138
 
139
SID_SR_Handler_Loop
140
	lfsr	FSR0, SIDL_SHADOW_BASE	; pointer to SIDL shadow registers
141
	lfsr	FSR1, SIDR_SHADOW_BASE	; pointer to SIDR shadow registers
142
	movlw	0xe0 | SIDx_V1_FRQ_L	; start address
143
	movwf	MIOS_PARAMETER1
144
 
145
	SET_BSR	SIDL_BASE
146
	IRQ_DISABLE			; disable interrupts to ensure consistency
147
	SID_SR_HANDLER_MACRO SIDx_V1_FRQ_L
148
	SID_SR_HANDLER_MACRO SIDx_V1_FRQ_H
149
	SID_SR_HANDLER_MACRO SIDx_V1_PW_L
150
	SID_SR_HANDLER_MACRO SIDx_V1_PW_H
151
	incf	MIOS_PARAMETER1, F	; skip CTRL register - transfered after OSC registers
152
	SID_SR_HANDLER_MACRO SIDx_V1_ENV_AD
153
	SID_SR_HANDLER_MACRO SIDx_V1_ENV_SR
154
 
155
	SID_SR_HANDLER_MACRO SIDx_V2_FRQ_L
156
	SID_SR_HANDLER_MACRO SIDx_V2_FRQ_H
157
	SID_SR_HANDLER_MACRO SIDx_V2_PW_L
158
	SID_SR_HANDLER_MACRO SIDx_V2_PW_H
159
	incf	MIOS_PARAMETER1, F	; skip CTRL register - transfered after OSC registers
160
	SID_SR_HANDLER_MACRO SIDx_V2_ENV_AD
161
	SID_SR_HANDLER_MACRO SIDx_V2_ENV_SR
162
 
163
	SID_SR_HANDLER_MACRO SIDx_V3_FRQ_L
164
	SID_SR_HANDLER_MACRO SIDx_V3_FRQ_H
165
	SID_SR_HANDLER_MACRO SIDx_V3_PW_L
166
	SID_SR_HANDLER_MACRO SIDx_V3_PW_H
167
	incf	MIOS_PARAMETER1, F	; skip CTRL register - transfered after OSC registers
168
	SID_SR_HANDLER_MACRO SIDx_V3_ENV_AD
169
	SID_SR_HANDLER_MACRO SIDx_V3_ENV_SR
170
 
171
#if ENABLE_SWINSID
172
	movlw	0xe0 | SIDx_SWINSID_V1_PHASE	; start address
173
	movwf	MIOS_PARAMETER1
174
	SID_SR_HANDLER_MACRO SIDx_SWINSID_V1_PHASE
175
	SID_SR_HANDLER_MACRO SIDx_SWINSID_V2_PHASE
176
	SID_SR_HANDLER_MACRO SIDx_SWINSID_V3_PHASE
177
	SID_SR_HANDLER_MACRO SIDx_SWINSID_V1_MODE
178
	SID_SR_HANDLER_MACRO SIDx_SWINSID_V2_MODE
179
	SID_SR_HANDLER_MACRO SIDx_SWINSID_V3_MODE
180
#endif
181
 
182
	IRQ_ENABLE			; temporary enable interrupts for reduced IRQ latency
183
	IRQ_DISABLE
184
 
185
	movlw	0xe0 | SIDx_V1_CTRL	; now transfer V1_CTRL register
186
	movwf	MIOS_PARAMETER1
187
	SID_SR_HANDLER_MACRO SIDx_V1_CTRL
188
	movlw	0xe0 | SIDx_V2_CTRL	; now transfer V2_CTRL register
189
	movwf	MIOS_PARAMETER1
190
	SID_SR_HANDLER_MACRO SIDx_V2_CTRL
191
	movlw	0xe0 | SIDx_V3_CTRL	; now transfer V3_CTRL register
192
	movwf	MIOS_PARAMETER1
193
	SID_SR_HANDLER_MACRO SIDx_V3_CTRL
194
 
195
	movlw	0xe0 | SIDx_FC_L	; transfer remaining registers
196
	movwf	MIOS_PARAMETER1
197
	SID_SR_HANDLER_MACRO SIDx_FC_L
198
	SID_SR_HANDLER_MACRO SIDx_FC_H
199
	SID_SR_HANDLER_MACRO SIDx_RES_FCHN
200
	SID_SR_HANDLER_MACRO SIDx_MODE_VOL
201
 
202
	;; check if phase sync has been requested
203
	SET_BSR	SID_BASE
204
	movf	SID_SE_PHASE_SYNC_REQ, W, BANKED
205
	bz	SID_SR_Handler_NoPhaseSync
206
SID_SR_Handler_PhaseSync
207
	;; if lead engine: variable phase, otherwise individual sync
208
	movff	SID_PATCH_BUFFER_SHADOW + SID_Ix_ENGINE, WREG
209
	andlw	0x03
210
	bnz	SID_SR_Handler_PhaseSync_M
211
SID_SR_Handler_PhaseSync_L
212
	rcall	SID_SR_VarPhase
213
  	rgoto	SID_SR_Handler_Loop	; update registers again
214
 
215
SID_SR_Handler_PhaseSync_M
216
	rcall	SID_SR_SyncPhase
217
 
218
SID_SR_Handler_NoPhaseSync
219
 
220
	;; sync with sound engine
221
	SET_BSR	SID_BASE
222
	clrf	SID_SE_SR_UPDATE_SYNC, BANKED
223
 
224
	;; enable interrupts again
225
	IRQ_ENABLE
226
 
227
	return
228
 
229
 
230
;; --------------------------------------------------------------------------
231
;;  Transfer register value to left (L), right (R) or both (B) SIDs
232
;;  IN: address | 0xe0 (!) in MIOS_PARAMETER1, value in WREG
233
;;      pointer to SIDL shadow registers in FSR0
234
;;      pointer to SIDR shadow registers in FSR1
235
;; --------------------------------------------------------------------------
236
SID_SR_TransferL
237
	movwf	MIOS_PARAMETER2			; store value in MIOS_PARAMETER2
238
	movf	MIOS_PARAMETER1, W		; store value in SIDL shadow register
239
	andlw	0x1f
240
	movff	MIOS_PARAMETER2, PLUSW0
241
 
242
	rcall	SID_SR_Write_Sub		; transfer value
243
 
244
	;; synchronize with rising edge of SID clock to avoid setup or hold violation
245
	;; note: due to pipeline effects, the "bcf" will be executed 3 instruction cycles after
246
	;; the polling loop. Therefore we are waiting for the falling edge
247
	btfss	PORTC, 2; wait for falling clock edge
248
	bra $-2
249
	btfsc	PORTC, 2
250
	bra $-2
251
	bcf	SID_SR_LAT_WR, SID_SR_PIN_WR	; enable write (MBHP_SID: chip select)
252
	bra	$+2				; to ensure compatibility with on-board oscillator,
253
	bra	$+2				; wait for 1.2 uS (> one SID clock cycle)
254
	bra	$+2
255
	bra	$+2
256
	bra	$+2
257
	bra	$+2
258
	bsf	SID_SR_LAT_WR, SID_SR_PIN_WR	; disable write (MBHP_SID: chip select)
259
	return
260
 
261
 
262
SID_SR_TransferR
263
	movwf	MIOS_PARAMETER2			; store value in MIOS_PARAMETER2
264
	movf	MIOS_PARAMETER1, W		; store value in SIDR shadow register
265
	andlw	0x1f
266
	movff	MIOS_PARAMETER2, PLUSW1
267
 
268
	rcall	SID_SR_Write_Sub		; transfer value
269
 
270
	;; synchronize with rising edge of SID clock to avoid setup or hold violation
271
	;; note: due to pipeline effects, the "bcf" will be executed 3 instruction cycles after
272
	;; the polling loop. Therefore we are waiting for the falling edge
273
	btfss	PORTC, 2; wait for falling clock edge
274
	bra $-2
275
	btfsc	PORTC, 2
276
	bra $-2
277
	bcf	SID_SR_LAT_WR2, SID_SR_PIN_WR2	; enable write (MBHP_SID: chip select)
278
	bra	$+2				; to ensure compatibility with on-board oscillator,
279
	bra	$+2				; wait for 1.2 uS (> one SID clock cycle)
280
	bra	$+2
281
	bra	$+2
282
	bra	$+2
283
	bra	$+2
284
	bsf	SID_SR_LAT_WR2, SID_SR_PIN_WR2	; disable write (MBHP_SID: chip select)
285
	return
286
 
287
 
288
SID_SR_TransferB
289
	movwf	MIOS_PARAMETER2			; store value in MIOS_PARAMETER2
290
	movf	MIOS_PARAMETER1, W		; store value in SIDL and SIDR shadow register
291
	andlw	0x1f
292
	movff	MIOS_PARAMETER2, PLUSW0
293
	movff	MIOS_PARAMETER2, PLUSW1
294
 
295
	rcall	SID_SR_Write_Sub		; transfer value
296
 
297
	;; synchronize with rising edge of SID clock to avoid setup or hold violation
298
	;; note: due to pipeline effects, the "bcf" will be executed 3 instruction cycles after
299
	;; the polling loop. Therefore we are waiting for the falling edge
300
	btfss	PORTC, 2; wait for falling clock edge
301
	bra $-2
302
	btfsc	PORTC, 2
303
	bra $-2
304
	bcf	SID_SR_LAT_WR, SID_SR_PIN_WR	; enable write (MBHP_SID: chip select)
305
	bcf	SID_SR_LAT_WR2, SID_SR_PIN_WR2	; enable write (MBHP_SID: chip select)
306
	bra	$+2				; to ensure compatibility with on-board oscillator,
307
	bra	$+2				; wait for 1.2 uS (> one SID clock cycle)
308
	bra	$+2
309
	bra	$+2
310
	bra	$+2
311
	bra	$+2
312
	bsf	SID_SR_LAT_WR, SID_SR_PIN_WR	; disable write (MBHP_SID: chip select)
313
	bsf	SID_SR_LAT_WR2, SID_SR_PIN_WR2	; disable write (MBHP_SID: chip select)
314
	return
315
 
316
 
317
;; --------------------------------------------------------------------------
318
;;  SID Write: write to SID register
319
;; --------------------------------------------------------------------------
320
SID_SR_Write_Sub
321
	;; SID signals:
322
	;; MIOS_PARAMETER2[7..0]: Data
323
	;; MIOS_PARAMETER1[4..0]: Address
324
	;; MIOS_PARAMETER1[5]   : Reset
325
	;; temporary used as counter: MIOS_PARAMETER3
326
 
327
        bcf     SID_SR_LAT_SCLK, SID_SR_PIN_SCLK	; clear clock
328
 
329
	;; superfast transfer with unrolled loop (takes some memory, but guarantees the
330
	;; lowest system load :)
331
SID_SR_WRITE_BIT MACRO reg, bit
332
	bcf	SID_SR_LAT_OUT, SID_SR_PIN_OUT	; set out pin depending on register content (reg.bit)
333
	btfsc	reg, bit
334
	bsf	SID_SR_LAT_OUT, SID_SR_PIN_OUT
335
        bsf     SID_SR_LAT_SCLK, SID_SR_PIN_SCLK	; rising clock edge
336
        bcf     SID_SR_LAT_SCLK, SID_SR_PIN_SCLK	; falling clock edge
337
	ENDM
338
 
339
	SID_SR_WRITE_BIT MIOS_PARAMETER2, 0
340
	SID_SR_WRITE_BIT MIOS_PARAMETER2, 1
341
	SID_SR_WRITE_BIT MIOS_PARAMETER2, 2
342
	SID_SR_WRITE_BIT MIOS_PARAMETER2, 3
343
	SID_SR_WRITE_BIT MIOS_PARAMETER2, 4
344
	SID_SR_WRITE_BIT MIOS_PARAMETER2, 5
345
	SID_SR_WRITE_BIT MIOS_PARAMETER2, 6
346
	SID_SR_WRITE_BIT MIOS_PARAMETER2, 7
347
 
348
	SID_SR_WRITE_BIT MIOS_PARAMETER1, 0
349
	SID_SR_WRITE_BIT MIOS_PARAMETER1, 1
350
	SID_SR_WRITE_BIT MIOS_PARAMETER1, 2
351
	SID_SR_WRITE_BIT MIOS_PARAMETER1, 3
352
	SID_SR_WRITE_BIT MIOS_PARAMETER1, 4
353
	SID_SR_WRITE_BIT MIOS_PARAMETER1, 5
354
	SID_SR_WRITE_BIT MIOS_PARAMETER1, 6
355
	SID_SR_WRITE_BIT MIOS_PARAMETER1, 7
356
 
357
        bsf     SID_SR_LAT_RCLK, SID_SR_PIN_RCLK	; latch SID values
358
	bcf	SID_SR_LAT_OUT, SID_SR_PIN_OUT	; clear out pin (standby)
359
        bcf     SID_SR_LAT_RCLK, SID_SR_PIN_RCLK	; release latch
360
 
361
	return
362
 
363
 
364
;; --------------------------------------------------------------------------
365
;;  Variable Oscillator Phase Offset for Lead Engine
366
;; --------------------------------------------------------------------------
367
SID_SR_VarPhase
368
	SET_BSR	SIDL_BASE
369
 
370
	;; temporary enable interrupts (especially to prevent MIDI receive buffer overflow)
371
	IRQ_ENABLE
372
	IRQ_DISABLE
373
 
374
	;; note: set the frequency to the maximum value (3.906kHz)
375
	;; this results into a period length of 256 uS
376
	;; now the offset between the oscillators can be adjusted by adding a n*1uS delay between the syncs
377
	movlw	0xe0 | SIDx_V1_FRQ_L
378
	movwf	MIOS_PARAMETER1
379
	movlw	LOW(65535)
380
	rcall	SID_SR_TransferB
381
	incf	MIOS_PARAMETER1, F
382
	movlw	HIGH(65535)
383
	rcall	SID_SR_TransferB
384
 
385
	movlw	0xe0 | SIDx_V2_FRQ_L
386
	movwf	MIOS_PARAMETER1
387
	movlw	LOW(65535)
388
	rcall	SID_SR_TransferB
389
	incf	MIOS_PARAMETER1, F
390
	movlw	HIGH(65535)
391
	rcall	SID_SR_TransferB
392
 
393
	movlw	0xe0 | SIDx_V3_FRQ_L
394
	movwf	MIOS_PARAMETER1
395
	movlw	LOW(65535)
396
	rcall	SID_SR_TransferB
397
	incf	MIOS_PARAMETER1, F
398
	movlw	HIGH(65535)
399
	rcall	SID_SR_TransferB
400
 
401
	;; change test flag -> gate
402
	bcf	SIDL_BASE + SIDx_V1_CTRL, 3, BANKED	; clear test flag
403
	bcf	SIDL_BASE + SIDx_V2_CTRL, 3, BANKED	; clear test flag
404
	bcf	SIDL_BASE + SIDx_V3_CTRL, 3, BANKED	; clear test flag
405
	bcf	SIDR_BASE + SIDx_V1_CTRL, 3, BANKED	; clear test flag
406
	bcf	SIDR_BASE + SIDx_V2_CTRL, 3, BANKED	; clear test flag
407
	bcf	SIDR_BASE + SIDx_V3_CTRL, 3, BANKED	; clear test flag
408
 
409
	;; set gate if sync was requested (accordingly test flag was set before)
410
	movff	SID_SE_PHASE_SYNC_REQ, WREG
411
	btfsc	WREG, 0
412
	bsf	SIDL_BASE + SIDx_V1_CTRL, 0, BANKED	; set gate flag
413
	btfsc	WREG, 1
414
	bsf	SIDL_BASE + SIDx_V2_CTRL, 0, BANKED	; set gate flag
415
	btfsc	WREG, 2
416
	bsf	SIDL_BASE + SIDx_V3_CTRL, 0, BANKED	; set gate flag
417
	btfsc	WREG, 3
418
	bsf	SIDR_BASE + SIDx_V1_CTRL, 0, BANKED	; set gate flag
419
	btfsc	WREG, 4
420
	bsf	SIDR_BASE + SIDx_V2_CTRL, 0, BANKED	; set gate flag
421
	btfsc	WREG, 5
422
	bsf	SIDR_BASE + SIDx_V3_CTRL, 0, BANKED	; set gate flag
423
 
424
	;; update registers
425
	movlw	0xe0 | SIDx_V1_CTRL	; now transfer V1_CTRL register
426
	movwf	MIOS_PARAMETER1
427
	SID_SR_HANDLER_MACRO SIDx_V1_CTRL
428
 
429
	;; add n*1uS delay
430
	movff	SID_PATCH_BUFFER_SHADOW + SID_Ix_L_OSC_PHASE, WREG
431
	addlw	14	; compensation
432
	skpnc
433
	movlw	255
434
	movwf	TMP1
435
SID_SR_VarPhase_Loop1
436
	nop
437
	nop
438
	nop
439
	nop
440
	nop
441
	nop
442
	nop
443
	decfsz	TMP1, F
444
	rgoto	SID_SR_VarPhase_Loop1
445
 
446
	movlw	0xe0 | SIDx_V2_CTRL	; now transfer V2_CTRL register
447
	movwf	MIOS_PARAMETER1
448
	SID_SR_HANDLER_MACRO SIDx_V2_CTRL
449
 
450
	;; add n*1uS delay
451
	movff	SID_PATCH_BUFFER_SHADOW + SID_Ix_L_OSC_PHASE, WREG
452
	addlw	14	; compensation
453
	skpnc
454
	movlw	255
455
	movwf	TMP1
456
SID_SR_VarPhase_Loop2
457
	nop
458
	nop
459
	nop
460
	nop
461
	nop
462
	nop
463
	nop
464
	decfsz	TMP1, F
465
	rgoto	SID_SR_VarPhase_Loop2
466
 
467
	movlw	0xe0 | SIDx_V3_CTRL	; now transfer V3_CTRL register
468
	movwf	MIOS_PARAMETER1
469
	SID_SR_HANDLER_MACRO SIDx_V3_CTRL
470
 
471
	;; clear sync requests
472
	SET_BSR	SID_BASE
473
	clrf	SID_SE_PHASE_SYNC_REQ, BANKED
474
 
475
	return
476
 
477
 
478
 
479
;; --------------------------------------------------------------------------
480
;;  Individual Oscillator Phase Reset for Multi, Bassline and Drum Engine
481
;; --------------------------------------------------------------------------
482
SID_SR_SyncPhase
483
	SET_BSR	SIDL_BASE
484
 
485
	;; change test flag -> gate
486
	movff	SID_SE_PHASE_SYNC_REQ, WREG
487
	btfsc	WREG, 0
488
	bcf	SIDL_BASE + SIDx_V1_CTRL, 3, BANKED	; clear test flag
489
	btfsc	WREG, 1
490
	bcf	SIDL_BASE + SIDx_V2_CTRL, 3, BANKED	; clear test flag
491
	btfsc	WREG, 2
492
	bcf	SIDL_BASE + SIDx_V3_CTRL, 3, BANKED	; clear test flag
493
	btfsc	WREG, 3
494
	bcf	SIDR_BASE + SIDx_V1_CTRL, 3, BANKED	; clear test flag
495
	btfsc	WREG, 4
496
	bcf	SIDR_BASE + SIDx_V2_CTRL, 3, BANKED	; clear test flag
497
	btfsc	WREG, 5
498
	bcf	SIDR_BASE + SIDx_V3_CTRL, 3, BANKED	; clear test flag
499
 
500
	;; set gate if sync was requested (accordingly test flag was set before)
501
	btfsc	WREG, 0
502
	bsf	SIDL_BASE + SIDx_V1_CTRL, 0, BANKED	; set gate flag
503
	btfsc	WREG, 1
504
	bsf	SIDL_BASE + SIDx_V2_CTRL, 0, BANKED	; set gate flag
505
	btfsc	WREG, 2
506
	bsf	SIDL_BASE + SIDx_V3_CTRL, 0, BANKED	; set gate flag
507
	btfsc	WREG, 3
508
	bsf	SIDR_BASE + SIDx_V1_CTRL, 0, BANKED	; set gate flag
509
	btfsc	WREG, 4
510
	bsf	SIDR_BASE + SIDx_V2_CTRL, 0, BANKED	; set gate flag
511
	btfsc	WREG, 5
512
	bsf	SIDR_BASE + SIDx_V3_CTRL, 0, BANKED	; set gate flag
513
 
514
	;; update registers
515
	movlw	0xe0 | SIDx_V1_CTRL
516
	movwf	MIOS_PARAMETER1
517
	SID_SR_HANDLER_MACRO SIDx_V1_CTRL
518
 
519
	movlw	0xe0 | SIDx_V2_CTRL
520
	movwf	MIOS_PARAMETER1
521
	SID_SR_HANDLER_MACRO SIDx_V2_CTRL
522
 
523
	movlw	0xe0 | SIDx_V3_CTRL
524
	movwf	MIOS_PARAMETER1
525
	SID_SR_HANDLER_MACRO SIDx_V3_CTRL
526
 
527
	;; clear sync requests
528
	SET_BSR	SID_BASE
529
	clrf	SID_SE_PHASE_SYNC_REQ, BANKED
530
 
531
	return