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44 tk 1
; $Id: sid_aout.inc 44 2008-01-30 21:39:30Z tk $
1 tk 2
;
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; AOUT driver for daisychained MAX525
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;
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; Special Variation of the official "aout.inc" module for
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; MIDIbox SID to achive best performance!
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; This module works with 2 MAX525 maximum, two pins
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; are refreshed at the same time, CS/DIN/SCLK pinning different,
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; interrupts are not blocked
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;
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; ==========================================================================
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;
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;  Copyright 1998-2007 Thorsten Klose (tk@midibox.org)
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;  Licensed for personal non-commercial use only.
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;  All other rights reserved.
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;
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; ==========================================================================
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;
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; The pins to which the first MBHP_AOUT module is connected have to be defined here:
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;
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#define SID_AOUT_LAT_CS		LATC	; The chip select pin CS#
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#define SID_AOUT_TRIS_CS	TRISC	; is connected to Port C.3
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#define SID_AOUT_PIN_CS		3	; (CANNOT be shared with other outputs!)
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;
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#define SID_AOUT_LAT_DIN	LATC	; The data input pin DIN
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#define SID_AOUT_TRIS_DIN	TRISC	; is connected to Port C.1
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#define SID_AOUT_PIN_DIN	1	; (can be shared with other outputs)
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;
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#define SID_AOUT_LAT_SCLK	LATC	; The shift clock input pin SCLK
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#define SID_AOUT_TRIS_SCLK	TRISC	; is connected to Port C.0
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#define SID_AOUT_PIN_SCLK	0	; (can be shared with other outputs)
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;
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;; --------------------------------------------------------------------------
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;;  FUNCTION: SID_AOUT_Init
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;;  DESCRIPTION: This function initializes all connected MAX525
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;;  IN:   -
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;;  OUT:  -
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;;  USES: BSR
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;; --------------------------------------------------------------------------
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SID_AOUT_Init
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	;; enable pin drivers
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	bcf	SID_AOUT_TRIS_CS, SID_AOUT_PIN_CS
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	bcf	SID_AOUT_TRIS_DIN, SID_AOUT_PIN_DIN
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	bcf	SID_AOUT_TRIS_SCLK, SID_AOUT_PIN_SCLK
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	;; deactivate chip select
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	bsf	SID_AOUT_LAT_CS, SID_AOUT_PIN_CS
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	;; clear the AOUT gate pins
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	SET_BSR	AOUT_GATE
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	clrf	AOUT_GATE, BANKED
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	;; set voltages to 0V
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	lfsr	FSR0, AOUT0_L
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	movlw	8
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	movwf	MIOS_PARAMETER3	; used as loop counter here
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SID_AOUT_InitVoutLoop
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	clrf	POSTINC0	; AOUTx_L
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	clrf	POSTINC0	; AOUTx_H
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	decfsz	MIOS_PARAMETER3, F
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	rgoto	SID_AOUT_InitVoutLoop
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	;; update the AOUT pins
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	rcall	SID_AOUT_Update
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	return
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;; --------------------------------------------------------------------------
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;;  FUNCTION: SID_AOUT_Load2SR
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;;  DESCRIPTION: This function loads two MAX525 shift registers at once
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;;  IN:   o low byte of first SR value in TMP1
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;;        o high byte of first SR value in TMP2
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;;        o low byte of second SR value in TMP3
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;;        o high byte of second SR value in TMP4
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;;  OUT:  -
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;;  USES: TMP[12345]
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;; --------------------------------------------------------------------------
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SID_AOUT_Load2SR
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        bcf	SID_AOUT_LAT_SCLK, SID_AOUT_PIN_SCLK	; clear clock
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	bcf	SID_AOUT_LAT_CS, SID_AOUT_PIN_CS	; activate chip select
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	;; NOTE: you will notice that the instructions are sometimes arranged
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	;; in a special order to ensure proper output signals - for example:
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	;; between a rising and a falling SCLK edge there is at least one
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	;; other instruction to ensure that the high pulse of the SCLK
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	;; is longer than 100 nS (the MAX525 datasheet specifies at least 40 nS)
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	movlw	32				; init loop counter
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	movwf	TMP5
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SID_AOUT_Load2SR_Loop
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	bcf	SID_AOUT_LAT_DIN, SID_AOUT_PIN_DIN	; set DIN depending on current MSB
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	btfsc	TMP4, 7
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	bsf	SID_AOUT_LAT_DIN, SID_AOUT_PIN_DIN
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	rlf	TMP1, F				; start to shift the 32-bit value
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	rlf	TMP2, F				; second step for the 32-bit shift
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	bsf	SID_AOUT_LAT_SCLK, SID_AOUT_PIN_SCLK	; rising clock edge
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	rlf	TMP3, F				; third step for the 32-bit shift
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	rlf	TMP4, F				; last step for the 32-bit shift
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	bcf	SID_AOUT_LAT_SCLK, SID_AOUT_PIN_SCLK	; falling clock edge
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	decfsz	TMP5, F				; loop 32 times
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	rgoto	SID_AOUT_Load2SR_Loop
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	bsf	SID_AOUT_LAT_CS, SID_AOUT_PIN_CS; deactivate chip select
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	return
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;; --------------------------------------------------------------------------
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;;  FUNCTION: SID_AOUT_Update
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;;  DESCRIPTION: refreshes the AOUT pins if AOUT values have been changed
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;;  OUT:  -
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;;  USES: TMP[12345] and MIOS_PARAMETER[123]
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;; --------------------------------------------------------------------------
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SID_AOUT_Update
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	lfsr	FSR0, AOUT0_L
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	lfsr	FSR1, AOUT4_L
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	clrf	MIOS_PARAMETER1		; used as loop counter here
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					; counts: 0x00, 0x40, 0x80, 0xc0 (optimization for code below)
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	movff	SID_LOCAL_ENS+SID_ENSx_AOUT_INVERTED, MIOS_PARAMETER3	; inversion flags for all 8 AOUTs
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SID_AOUT_Update_Loop
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	clrf	MIOS_PARAMETER2		; bit 0 indicates if one of the SRs has to be updated
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	IRQ_DISABLE			; disable interrupts to ensure data consistency
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	;; first SR
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	;; commands to load and update the DAC register:
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	;; A1=channel number[1], A0=channel number[0], C1=1, C0=1
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	movf	POSTINC0, W		; transfer low/high byte of first SR to TMP[12]
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	btfsc	MIOS_PARAMETER3, 0; invert if inversion flag is set
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	xorlw 0xff
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	movwf	TMP1
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	movf	INDF0, W
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	andlw	0x0f
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	btfsc	MIOS_PARAMETER3, 0; invert if inversion flag is set
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	xorlw 0x0f
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	iorlw	0x30
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	iorwf	MIOS_PARAMETER1, W
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	movwf	TMP2
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	btfss	INDF0, 7		; notify if AOUT value has been changed
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	bsf	MIOS_PARAMETER2, 0
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	;; second SR
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	;; commands to load and update the DAC register:
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	;; A1=channel number[1], A0=channel number[0], C1=1, C0=1
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	movf	POSTINC1, W		; transfer low/high byte of second SR to TMP[34]
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	btfsc	MIOS_PARAMETER3, 4; invert if inversion flag is set
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	xorlw 0xff
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	movwf	TMP3
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	movf	INDF1, W
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	andlw	0x0f
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	btfsc	MIOS_PARAMETER3, 4; invert if inversion flag is set
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	xorlw 0x0f
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	iorlw	0x30
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	iorwf	MIOS_PARAMETER1, W
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	movwf	TMP4
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	btfss	INDF1, 7		; notify if AOUT value has been changed
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	bsf	MIOS_PARAMETER2, 0
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	IRQ_ENABLE			; enable interrupts
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	;; load SRs if at least one of the AOUT values has been changed
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	BRA_IFCLR MIOS_PARAMETER2, 0, ACCESS, SID_AOUT_Update_Loop_Next
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	rcall	SID_AOUT_Load2SR
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	;; notify that upload has been done
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	bsf	INDF0, 7
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	bsf	INDF1, 7
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SID_AOUT_Update_Loop_Next
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	;; increment to next low bytes
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	movf	POSTINC0, W
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	movf	POSTINC1, W
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	;; shiftright inversion flags
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	rrf	MIOS_PARAMETER3, F
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	;; increment 0x40 to loop counter until it reaches 0x00 again
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	movlw	0x40
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	addwf	MIOS_PARAMETER1, F
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	bnz	SID_AOUT_Update_Loop
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SID_AOUT_Update_Gates
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	;; do nothing if gate bits have not been changed
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	SET_BSR	AOUT_GATE
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	movf	AOUT_GATE, W, BANKED
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	xorwf	AOUT_GATE_SHADOW, W, BANKED
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	bz	SID_AOUT_UpdateGates_End
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	IRQ_DISABLE			; disable interrupts to ensure data consistency
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	;; commands to set the UPO:
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	;; UPO=low:  A1=0, A0=0, C1=1, C0=0
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	;; UPO=high: A1=0, A0=1, C1=1, C0=0
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	clrf	TMP1			; transfer low/high byte to first SR to TMP[12]
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	movlw	0x20
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	btfsc	AOUT_GATE, 0, BANKED
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	iorlw 0x40
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	movwf	TMP2
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	;; commands to set the UPO:
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	;; UPO=low:  A1=0, A0=0, C1=1, C0=0
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	;; UPO=high: A1=0, A0=1, C1=1, C0=0
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	clrf	TMP3			; transfer low/high byte to second SR to TMP[34]
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	movlw	0x20
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	btfsc	AOUT_GATE, 1, BANKED
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	iorlw 0x40
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	movwf	TMP4
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210
	;; load SRs and exit
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	rcall	SID_AOUT_Load2SR
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	;; optionally forward to DOUT
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#if DEFAULT_EXT_SWITCH_DOUT
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	movff	AOUT_GATE, MIOS_PARAMETER1
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	movlw	(DEFAULT_EXT_SWITCH_DOUT-1) & 0x0f
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	call	MIOS_DOUT_SRSet
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#endif
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220
	;; optionally forward to J5
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	SET_BSR	AOUT_GATE
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#if DEFAULT_J5_FUNCTION == 3
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	movf	AOUT_GATE, W, BANKED
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	call	J5_DOUT_Set
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#endif
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227
	;; update shadow register
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	movf	AOUT_GATE, W, BANKED
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	movwf	AOUT_GATE_SHADOW, BANKED
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	IRQ_ENABLE			; enable interrupts
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SID_AOUT_UpdateGates_End
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SID_AOUT_Update_End
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	return